Encoder AND Decoder

In short: An encoder compresses 2ⁿ one-hot input lines into an n-bit binary code, while a decoder does the opposite and expands an n-bit code into 2ⁿ mutually exclusive output lines, so they are inverse functions used for compaction and for selection respectively.

Two blocks, opposite directions

Both blocks are pure combinational logic: no clock, no memory, outputs depend only on present inputs. What separates them is the direction of conversion. A decoder takes a dense code and turns it into a sparse, one-hot signal. A encoder takes a sparse, one-hot signal and turns it into a dense code. If you chain a decoder into an encoder of the same width, you get your original binary value back, which is the easiest way to remember that they are inverses.

The decoder: truth table and equations

A 2-to-4 decoder with an active-high enable E asserts exactly one of four outputs. When E = 0 all outputs are 0, which is what lets you cascade decoders.

Each output is simply a minterm: Y0 = E·A1'·A0', Y1 = E·A1'·A0, Y2 = E·A1·A0', Y3 = E·A1·A0. That is one 3-input AND gate per output plus two inverters. An n-to-2ⁿ decoder needs 2ⁿ AND gates of n+1 inputs, so cost grows exponentially, and wide decoders are built in two stages (predecode, then final AND) to keep fan-in and delay under control.

Key fact: A decoder generates all minterms of its inputs, so any Boolean function of n variables can be built from one n-to-2ⁿ decoder plus an OR gate that collects the minterms where the function is 1.

The encoder: truth table and its weakness

A 4-to-2 encoder assumes exactly one input is high at any moment.

The equations are A1 = D2 + D3 and A0 = D1 + D3: each output bit is an OR of every input whose index has that bit set. Notice what is missing. All-zeros gives 00, identical to D0 being pressed, so you cannot tell "nothing active" from "D0 active". And if D1 and D2 are high together, the OR gates return 11, which wrongly reports D3. This is why real designs use a priority encoder that ranks inputs and adds a valid output, usually called V or GS.

Key fact: A plain encoder has 2ⁿ input combinations but only 2ⁿ of them are legal out of 2²ⁿ, so almost its entire input space is undefined. Never use one where more than one request can arrive at once.

Side-by-side comparison

Watch it work

The animation below steps a 2-bit address through 00, 01, 10, 11. Exactly one output lights up each time, which is the defining decoder behaviour.

Where each one is used in real silicon

• Memory address decoding: a 1 K x 8 SRAM has 10 address bits, so the row decoder is effectively 10-to-1024 (split into row and column halves to keep it practical). Each word line is one decoder output.
• Chip select in SoCs: the upper address bits are decoded to enable one peripheral, such as UART or GPIO, per bus transaction. A 3-to-8 part like the classic 74HC138 gives eight select lines from three address bits.
• Seven-segment drivers: a BCD-to-seven-segment decoder (74HC47 family) expands 4 bits into 7 segment lines.
• Keypad and interrupt encoding: a 16-key keypad needs only 4 bits out through an encoder; an interrupt controller encodes up to 8 IRQ lines into a 3-bit vector, with priority, as in the 74HC148.
• Instruction decode: a CPU's control unit decodes opcode fields into enable signals for the ALU, register file and load/store paths.

Writing them in RTL and what synthesis does

In Verilog, a decoder is naturally a shift or a case statement:

// 2-to-4 decoder with enable
assign y = e ? (4'b0001 << a) : 4'b0000;

// 4-to-2 priority-style encoder
always @(*) begin
  casez (d)
    4'b1???: a = 2'd3;
    4'b01??: a = 2'd2;
    4'b001?: a = 2'd1;
    default: a = 2'd0;
  endcase
end

Tools such as Synopsys Design Compiler, Cadence Genus and Siemens Questa all recognise these patterns. Genus and Design Compiler map the decoder to AND/NOR trees and, for wide address decoders, may restructure them for timing. A casez with overlapping patterns infers priority, whereas a unique case tells synthesis the inputs are one-hot, removing the priority chain and saving area. Static timing on a large decoder in a memory path is often critical, so decoders are one of the first places a physical designer looks when a read-access path fails. Our multiplexer and demultiplexer article shows how a demux is just a decoder whose enable carries the data. Teams at Avecas run exactly these structures through RTL-to-GDS flows daily.

Interview tip: If asked "how many 2-to-4 decoders build a 4-to-16 decoder?", the answer is five: four drive the outputs in groups of four and one predecodes the upper two bits to drive their enables.

Common mistakes

• Using a non-priority encoder with simultaneous requests, giving silently wrong codes.
• Forgetting the valid flag, so "no input" looks like input 0.
• Ignoring glitches: when an address changes from 01 to 10, both bits switch and a decoder output can pulse briefly. Do not feed decoder outputs straight to asynchronous clears or clock gates; register or gate them with a clean enable.
• Mixing active-low and active-high conventions between decoder outputs and chip selects.

Want to build and simulate these blocks yourself? Our ChipXpert training programs take the same ideas into full RTL, verification and physical design projects.

Ready to go beyond truth tables? Explore the CourseTron digital electronics lessons in our courses and practise encoders, decoders and more with guided exercises.

Frequently asked questions

Is a decoder the inverse of an encoder?

Functionally yes for valid one-hot inputs: decoding a binary code and then encoding the result returns the same code. The reverse chain fails if the encoder sees multiple active lines.

Why does a decoder have an enable input?

The enable forces all outputs inactive, which allows several small decoders to be cascaded into a larger one and lets a bus controller disable all selects during idle cycles.

How many outputs does a 3-to-8 decoder have and why?

Eight, because three input bits have 2³ = 8 combinations and each combination activates a different output line.

Can a decoder implement any logic function?

Yes. Connect the decoder outputs corresponding to the function's minterms to an OR gate. For an n-variable function this uses one n-to-2ⁿ decoder and one OR.