In short: A multiplexer (MUX) uses n select lines to route exactly one of 2n data inputs to a single output, and because it can implement any Boolean function by wiring variables to its selects and constants or literals to its data inputs, it is a universal logic element.
What a multiplexer actually does
A multiplexer is a digital switch controlled by data. It has 2n data inputs, n select lines and one output. The binary value on the select lines picks which input appears at the output; every other input is ignored. A 2:1 MUX needs one select bit, a 4:1 needs two, an 8:1 needs three, and a 16:1 needs four. Width of the select bus is therefore log2 of the number of inputs.
The classic mental model is a railway junction: many tracks come in, one goes out, and the points (select lines) decide which track is connected. Unlike a bus with tri-state drivers, a MUX is purely combinational: change a select or the chosen data input and the output follows after a propagation delay, with no clock involved. Its mirror image, which spreads one input over many outputs, is covered in our demultiplexer article.
Truth table and Boolean equation
For a 4:1 MUX with data inputs I0 to I3 and selects S1 S0, the table is compact if you let the data inputs appear symbolically instead of expanding all six input variables into 64 rows.
| S1 | S0 | Y |
|---|---|---|
| 0 | 0 | I0 |
| 0 | 1 | I1 |
| 1 | 0 | I2 |
| 1 | 1 | I3 |
The sum-of-products form is Y = S1'·S0'·I0 + S1'·S0·I1 + S1·S0'·I2 + S1·S0·I3. Each product term is a decoded select combination ANDed with its data input, and the OR gate merges them. Only one product term can be non-zero at any time, which is why this works as a clean selector.
Key fact: A 2n:1 MUX has exactly 2n AND terms of (n + 1) inputs each, feeding one 2n-input OR. A 4:1 therefore needs four 3-input ANDs, a 4-input OR and two inverters.
Gate-level design
The 2:1 MUX is the building block: Y = S'·A + S·B. It needs one inverter, two 2-input ANDs and one OR, so four gates, with a worst-case path of inverter, AND, OR. Larger MUXes can be built two ways. A flat implementation uses the SOP above with wide gates; a tree implementation cascades 2:1 stages. An 8:1 MUX as a tree uses seven 2:1 MUXes (four in the first level on S0, two on S1, one on S2), and the same S0 line fans out to four cells, so buffering matters.
In CMOS silicon, standard-cell libraries rarely build MUXes from AND-OR gates. They use transmission gates: an NMOS and PMOS pair in parallel that passes both logic levels without a threshold drop. A transmission-gate 2:1 MUX takes about 12 transistors including select inverters, versus roughly 16 for the AND-OR version, and is faster. Synthesis tools such as Synopsys Design Compiler or Cadence Genus map your RTL to the library's MUX2/MUX4 cells when timing and area say it pays off.
Watch it work
The MUX as a universal logic element
Any n-variable function can be implemented with a 2n:1 MUX by tying the variables to the select lines and each data input to 0 or 1 following the truth table. A smarter trick cuts the size in half: use a 2n-1:1 MUX, drive n-1 variables onto the selects, and feed the last variable (or its complement, or a constant) into the data inputs.
Example: implement F(A,B,C) = Σm(1,2,6,7) with a 4:1 MUX, A and B on the selects.
- AB = 00: minterms 0 and 1 exist as rows; only m1 is in F, so F = C, giving I0 = C.
- AB = 01: only m2 is in F (C = 0), so F = C', giving I1 = C'.
- AB = 10: neither m4 nor m5 is in F, so I2 = 0.
- AB = 11: both m6 and m7 are in F, so I3 = 1.
One 4:1 MUX and a single inverter replace a handful of gates. A 2-input XOR is just a 2:1 MUX with A on the select, B on I0 and B' on I1. NOT, AND, OR are equally easy: AND(A,B) is a 2:1 MUX with A selecting between 0 and B. That functional completeness is exactly why MUXes are called universal.
Key fact: This is not just theory. A Xilinx 7-series 6-input LUT is physically a 64:1 MUX whose data inputs are SRAM configuration bits and whose selects are the six logic inputs. Every FPGA gate you ever "wrote" lands in a tree of multiplexers.
Practical design issues
- Glitches. A 2:1 AND-OR MUX with A = B = 1 can briefly output 0 when S toggles, because S' and S cross at different times. This is a static-1 hazard; the fix is the redundant consensus term A·B added to the equation. Synthesis tools typically do not add it, so never use a MUX output as an asynchronous clock or reset.
- Clock muxing. Selecting between two clocks needs a glitch-free clock-gating mux with synchronised enables, not a bare MUX. STA tools such as Synopsys PrimeTime flag unsafe clock muxes.
- Delay. Depth grows as log2 N for a tree, so a 32:1 selector is five 2:1 levels; at about 50 ps per level in a modern node that is roughly 250 ps before wiring.
- One-hot selects. When select lines are already one-hot (as from an arbiter), an AND-OR structure is cheaper than binary decode and faster.
MUXes in Verilog
// 4:1 mux, behavioural
module mux4 (input [3:0] d, input [1:0] s, output y);
assign y = d[s];
endmodule
// 2:1 mux, ternary
assign y = sel ? b : a;Both infer MUX cells. A frequent bug is an incomplete case inside always @*, which infers a latch instead of a MUX; always add a default. Lint tools (Siemens Questa Lint, Synopsys SpyGlass) catch it. Interview favourites: build a 4:1 from 2:1 MUXes, implement a full adder with two 4:1 MUXes (sum selects on A,B with C and C' data; carry with 0, C, C, 1), and explain why a MUX with tied inputs reduces to a gate. Skills like these are drilled in our combinational logic design guide, and professional cohorts at ChipXpert's VLSI training programs apply them in RTL labs.
Ready to go beyond selectors? Build, simulate and synthesise MUX-based designs in the hands-on CourseTron digital electronics courses.
Frequently asked questions
How many select lines does a 16:1 multiplexer need?
Four, because 24 = 16. In general n = log2(number of inputs).
What is the difference between a MUX and a demultiplexer?
A MUX chooses one of many inputs for one output; a demultiplexer routes one input to one of many outputs. A decoder is a demultiplexer whose data input is held at logic 1.
Can a multiplexer implement any logic function?
Yes. A 2n:1 MUX realises any n-variable function directly, and a 2n-1:1 MUX can do it when the extra variable is fed into the data inputs.
Why does my MUX output glitch?
When two data inputs are both 1 and the select changes, the AND-OR structure can briefly drop to 0 (static-1 hazard). Adding the consensus term, or using a transmission-gate cell, removes it.