Demultiplexer

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In short: a demultiplexer (demux) steers one data input to exactly one of 2ⁿ outputs chosen by n select lines, and it is logically identical to an n-to-2ⁿ decoder whose enable pin carries the data.

What a demultiplexer actually does

A multiplexer funnels many inputs into one wire. A demultiplexer is its mirror image: one data line fans out to one of several destinations, and every other destination sits at a quiet, inactive level. Think of a railway switching yard. The train (data) is always the same; the points (select lines) decide which track receives it.

A 1-to-4 demux has one data input D, two select lines S1 S0 and four outputs Y0 to Y3. In general, n select lines address 2ⁿ outputs, so 1-to-8 needs three selects and 1-to-16 needs four. The selected output copies D; all others stay at logic 0 (or 1 for active-low parts).

Truth table and Boolean equations

Each row has exactly one live output. Read the columns and you get the four equations in the figure above. Notice the pattern: every equation is a three-input AND of D with a minterm of S1 and S0. That observation is the whole secret of this article.

Key fact: a 1-to-2ⁿ demux needs 2ⁿ AND gates of (n+1) inputs each, plus n inverters shared across them. A 1-to-8 needs eight 4-input ANDs.

Demux equals decoder with enable

An n-to-2ⁿ decoder with an enable input E produces Y_i = E · (minterm i of the inputs). Replace E with D and the decoder's address inputs with the select lines, and you have written the demux equations exactly. There is no hardware difference; only the datasheet label changes. If D = 0, every output is 0 regardless of select, just as a disabled decoder outputs nothing.

The classic part is the 74HC138, a 3-to-8 decoder with three enables (G1 active high, G2A and G2B active low) and active-low outputs. Feed data into G2A with G1 tied high and G2B tied low, and it acts as a 1-to-8 demux whose selected output is the inverse of D. Likewise the 74HC139 contains two independent 2-to-4 decoders, so it is two 1-to-4 demuxes in one package.

Key fact: the 74HC138 has outputs that are active low, so the selected line goes low when the data input is asserted. Forgetting this polarity is the most common bench mistake.

Watch it route a bit

In the animation below, the select lines are fixed at S1 S0 = 10, so the data pulse travels to Y2 and lights it while the other outputs stay dark.

Building larger demuxes

You rarely need a monolithic 1-to-16. A 1-to-16 can be a tree: the first 1-to-4 stage uses S3 S2 to pick one of four second-stage demuxes, and each of those uses S1 S0. That costs five 1-to-4 cells (20 outputs of which 16 are used), but in a two-stage tree the data passes through only two gate levels. Alternatively, a 4-to-16 decoder with enable does it in one level with sixteen 5-input ANDs. The trade-off is fan-in versus depth: wide ANDs are slow in CMOS because stacked NMOS transistors raise resistance, so synthesis tools usually split them into NAND/NOR trees anyway.

The same logic underpins memory. A 1K-word SRAM address decoder is effectively a demux that routes a "word-line enable" pulse to exactly one of 1024 rows. Row decoders are almost always predecoded: 10 address bits become two 5-to-32 groups, whose outputs are ANDed pairwise, cutting transistor count and delay.

Describing it in RTL

module demux1to4 (
  input  wire       d,
  input  wire [1:0] sel,
  output reg  [3:0] y
);
  always @* begin
    y = 4'b0000;        // default avoids latches
    y[sel] = d;
  end
endmodule

The default assignment on the first line matters. Without it, y keeps its old value for unselected bits and synthesis infers latches. Tools such as Synopsys Design Compiler, Cadence Genus and Siemens Questa (lint) all flag this. Design Compiler maps the code to a decoder-plus-AND structure, and in a standard-cell library it often lands on NOR2/NAND3 cells with inverted selects rather than literal AND gates.

Interviewers love one follow-up: "what happens if sel changes while d is 1?" Because sel and d come through different paths, the old output can drop and the new one rise at slightly different times, creating a glitch or a brief overlap where two outputs are high. That is a static hazard on a multi-bit transition (01 to 10 flips both select bits). If the outputs drive clock gates or write strobes, register the select lines first, or use a Gray-coded sequence.

Key fact: never use raw demux outputs as asynchronous clocks or reset lines. Use a synchronous enable, or an ICG (integrated clock-gating) cell, and let static timing in PrimeTime or Tempus check it.

Where demuxes show up in real designs

• Memory write-enable steering: a write strobe is routed to one register among many in a register file.
• Serial-to-parallel distribution: a time-division stream is split into channels, using a counter as the select.
• Bus address decode: an AXI interconnect uses upper address bits to select a peripheral's chip-select.
• Display scanning: multiplexed seven-segment displays enable one digit at a time.

Once you see a demux as "decoder plus data," decoder design and bus decoding stop feeling like separate topics. If you want guided practice with timing waveforms and RTL labs, the CourseTron courses cover this end to end. For hands-on lab and placement training in India, ChipXpert's VLSI training programmes are a natural next step.

Interview traps

• "Is a demux the inverse of a mux?" Functionally it reverses the data direction, but it is not a mathematical inverse; the mux discards unselected inputs, the demux drives zeros.
• "Can I build a demux from a mux?" Not directly without extra logic; a decoder with enable is the natural implementation.
• "How many 2-input gates for a 1-to-4?" Two inverters plus four 3-input ANDs, or equivalently eight 2-input ANDs and two inverters if you restrict fan-in.

Ready to go deeper? Explore the Digital Electronics track in the CourseTron courses and build decoders, demuxes and memory decoders in real RTL labs.

Frequently asked questions

Is a demultiplexer the same as a decoder?

Electrically, yes. A decoder with an enable input behaves exactly like a demux when you treat the enable as the data input. The naming just reflects intent: decoders identify an address, demuxes route data.

How many select lines does a 1-to-16 demux need?

Four, since 2⁴ = 16. In general the count is log₂ of the number of outputs.

What do unselected outputs do?

They stay at their inactive level: logic 0 for active-high parts and logic 1 for active-low parts such as the 74HC138.

Can a demux cause glitches?

Yes. When more than one select bit changes at once, outputs can briefly overlap or flicker. Register the select lines or use Gray-coded selects when the outputs drive strobes.