Decoder

In short: A decoder takes an n-bit binary code and asserts exactly one of 2ⁿ output lines, and an enable input lets you switch the whole block on or off, which is precisely how a CPU turns a few high address bits into chip-select signals for memory and peripherals.

What a decoder actually does

A binary decoder converts a compact code into a one-hot code. Feed an n-bit input and it drives one of 2ⁿ outputs active while every other output stays inactive. A 2-to-4 decoder has two inputs and four outputs, a 3-to-8 has three inputs and eight outputs, and a 4-to-16 has four inputs and sixteen outputs. The output count doubles with every added input, which is why decoders are the natural hardware answer to the question "which one of these N things is being addressed right now?"

Internally each output is simply a minterm of the inputs. For a 2-to-4 decoder with inputs A1 and A0, output Y0 = A1'·A0', Y1 = A1'·A0, Y2 = A1·A0' and Y3 = A1·A0. That means n inverters plus 2ⁿ AND gates, each with n inputs. Every possible input combination activates exactly one AND gate, so no two outputs can ever be active together. That mutual exclusivity is the property the rest of the system depends on.

Truth table and the enable input

The enable pin is what turns a pure combinational decoder into a usable system component. When EN = 0 every output is forced inactive regardless of A1 and A0. When EN = 1 the decoder behaves normally. In the table below, X means don't care.

Key fact: with EN = 0 the outputs are all inactive, so "no device selected" is a legal state. Without an enable pin you could never express it.

Real parts add one wrinkle: polarity. The classic 74HC139 (dual 2-to-4) and 74HC138 (3-to-8) have active-low outputs, meaning the selected line goes to 0 and the rest sit at 1. This suits chip-select pins, which are almost always active-low (CS#, CE#). The 74HC138 also has three enables, G1 (active-high) and G2A#, G2B# (active-low), so the part is on only when G1 = 1 and both others are 0. Three enables let you combine address bits and a bus-cycle strobe without extra gates. We walk through this part in detail in the 3-to-8 decoder article.

The decoder as a demultiplexer

Here is a trick interviewers love. Hold the select inputs as the "destination" and treat EN as a data input. When EN is 1, the addressed output goes active; when EN is 0 it stays inactive. The data bit has been routed to exactly one of 2ⁿ outputs, which is a 1-to-2ⁿ demultiplexer. That is why datasheets often label the same silicon "decoder/demultiplexer". The reverse operation, selecting one of many inputs, is a multiplexer, covered in our multiplexer guide.

Role in address decoding

A processor presents an address on its bus, and many devices hang on that bus: ROM, RAM, a UART, a timer. Each device has far fewer address pins than the CPU. A 16 KB ROM needs only 14 address lines (2¹⁴ = 16,384), so the remaining high lines must decide whether this ROM is the one being accessed. A decoder does that job.

Take a CPU with a 16-bit address bus (64 KB space). Feed A15 and A14 into a 2-to-4 decoder. Each output now owns a 16 KB block: Y0 covers 0x0000 to 0x3FFF, Y1 covers 0x4000 to 0x7FFF, Y2 covers 0x8000 to 0xBFFF and Y3 covers 0xC000 to 0xFFFF. Connect Y0 to ROM chip-select, Y1 to RAM, Y2 to an I/O bridge, and the lower 14 address lines go straight to every device in parallel. The decoder guarantees only one device ever drives the data bus, avoiding bus contention.

Key fact: a decoder using only some address bits gives partial decoding, where a device shows up at several mirrored addresses. Full decoding uses every upper bit, costs more gates, and removes the aliasing.

The enable input earns its keep here. Wire the CPU's memory-request or I/O-request strobe to EN, and the decoder only asserts a chip-select while a real bus cycle is in progress, not while the address bus is merely changing.

Seeing it in motion

The animation below counts the input from 00 to 11 and shows the single active output following it. Notice that one lamp is lit at any instant, never two.

Scaling up: decoder trees and predecoding

A 6-to-64 decoder built as 64 six-input AND gates is wasteful and slow, because wide gates have poor drive. Designers split it. Two 3-to-8 decoders produce 8 lines each, then 64 two-input ANDs combine one line from each group. This predecode scheme cuts gate fan-in from six to two and shares the inverters. SRAM row decoders and register-file read ports use the same structure, often with the final AND merged into the wordline driver. Cascading is also common on boards: a 74HC138 output can drive the enable of a second 74HC138, so two parts give a 4-to-16 decoder.

Timing matters too. If two address bits change at nearly the same instant, the decoder can briefly pulse a wrong output, a glitch caused by unequal path delays. Gating with EN, driven by a clean strobe that rises only after the address settles, hides the glitch from the devices.

Decoders in RTL and synthesis

In Verilog you rarely instantiate gates. A shift or a case statement describes the decoder, and synthesis tools such as Synopsys Design Compiler or Cadence Genus map it to cells.

module dec2to4 (input en, input [1:0] a, output reg [3:0] y);
  always @* begin
    y = 4'b0000;            // default avoids inferred latches
    if (en) y[a] = 1'b1;    // one-hot output
  end
endmodule

The default assignment on the first line matters. Omit it and a missed branch makes the tool infer a latch, a classic lint failure flagged by Siemens Questa and Synopsys SpyGlass. In an SoC, the same logic appears as the address decoder inside an AXI or APB interconnect, where wide base-address comparators generate peripheral selects. If you want to see this kind of design work done professionally, Avecas design services covers RTL and physical design for such blocks.

Key fact: for n inputs a decoder needs 2ⁿ outputs, so a 10-bit decode already means 1,024 lines. Large decoders are always built in stages, never as one flat AND plane.

Common interview questions

• How many 3-to-8 decoders build a 5-to-32? Four, plus one 2-to-4 driving their enables.
• Implement a full adder with a 3-to-8 decoder: the sum is the OR of minterms 1, 2, 4, 7 and the carry is the OR of 3, 5, 6, 7.
• What is the difference from an encoder? An encoder compresses 2ⁿ one-hot lines back into n bits; see the encoder article.

Want to design, simulate and verify these blocks yourself? Explore the hands-on CourseTron digital electronics courses, and for placement-focused VLSI training see ChipXpert.

Frequently asked questions

How many outputs does an n-input decoder have?

It has 2ⁿ outputs. Two inputs give four outputs, three give eight and four give sixteen.

Why do decoders have an enable input?

Enable forces all outputs inactive, which allows cascading to build bigger decoders, qualifying outputs with a bus strobe, and using the decoder as a demultiplexer.

What is the difference between full and partial address decoding?

Full decoding checks every address bit so each device appears at one address. Partial decoding ignores some bits, saving gates but creating mirrored copies of the device across the map.

Why are decoder outputs usually active-low?

Chip-select inputs on memories and peripherals are almost always active-low, so a 74HC138 or 74HC139 style output connects directly without extra inverters.