BCD to 7 Segment Decoder

In short: a BCD-to-7-segment decoder is a 4-input, 7-output combinational circuit whose outputs a to g are minimised sum-of-products functions, with input codes 10 to 15 treated as don’t-cares, followed by current-limited drivers matched to a common-anode or common-cathode display.

What the decoder actually does

A seven-segment digit has seven LEDs labelled a (top) clockwise to f, with g in the middle. A binary-coded decimal digit arrives as four bits, A (MSB) to D (LSB). The decoder converts those four bits into seven on/off commands. It is pure combinational logic: no clock, no memory, and the output depends only on the present input. If you have met the general idea in our decoder article, note the difference: an n-to-2ⁿ decoder is one-hot, while this one is an encoding converter whose outputs overlap heavily (the digit 8 lights everything).

The segment truth table

The table below uses active-high outputs for a common-cathode display (1 = lit). Two conventions matter in interviews: whether 6 and 9 carry their tails (segment a on for 6, segment d on for 9), and whether 7 has the extra f segment. We use tails on 6 and 9, and a three-segment 7, which is the usual textbook and 7447 style.

Key fact: only 10 of 16 input combinations are legal BCD. The six unused codes give you free don’t-care minterms, which shrink every segment equation.

K-map minimisation, segment by segment

Take segment a. It is off only for digits 1 and 4, so it is easiest to look for a few large groups of ones. Rows 11xx are all don’t-care and the A=1 rows have a 1 at 8 and 9, so the whole A half collapses to the single literal A. The remaining ones form C (digits 2, 3, 6, 7), B·D (5, 7) and B′·D′ (0, 8). The result is a = A + C + BD + B′D′.

Doing the same exercise for the rest gives the standard minimal set (prime marks denote complement):

• a = A + C + BD + B′D′
• b = B′ + C′D′ + CD
• c = B + C′ + D
• d = A + B′D′ + B′C + CD′ + BC′D
• e = B′D′ + CD′
• f = A + C′D′ + BC′ + BD′
• g = A + BC′ + B′C + CD′

Spot-check one: digit 6 is 0110. Segment e = CD′ = 1·1 = 1, correct, while segment b = B′ + C′D′ + CD = 0 + 0 + 0 = 0, also correct because 6 has no top-right bar. Always verify against the truth table row by row; a single wrong cell in a K-map is the most common exam error.

Key fact: segment c is the cheapest at three single literals ORed (B + C′ + D); segment d is the most expensive with five product terms, so it dominates the critical path and gate count.

Shared terms and what synthesis tools do

Minimising each output alone is not optimal. Terms such as C′D′ (in b and f), B′D′ (in a, d and e) and CD′ (in d, e and g) appear repeatedly, so a multi-output minimiser shares them. Classic tools such as Espresso do this; in a real flow you would simply write a case statement in Verilog and let Synopsys Design Compiler, Cadence Genus or the FPGA mapper in Xilinx Vivado find the sharing. With four inputs, the whole decoder fits in seven 4-input LUTs on an FPGA, or a ROM of 16 words by 7 bits. In RTL, the don’t-cares are expressed with default: seg = 7'bxxxxxxx;, which is exactly the freedom the tool exploits. A common pitfall is replacing x with a blank pattern for debug and then wondering why area grew by about 20 percent.

always @(*) begin
  case (bcd)
    4'd0: seg = 7'b1111110; // abcdefg
    4'd1: seg = 7'b0110000;
    4'd2: seg = 7'b1101101;
    // ... digits 3 to 9 ...
    default: seg = 7'bxxxxxxx;
  endcase
end

Watch it in motion

Driving the display correctly

Logic is the easy half. A red LED drops about 2 V at 10 mA, so on a 5 V rail each segment needs (5 − 2) / 0.01 = 300 Ω; the nearest standard 330 Ω gives roughly 9 mA. Never share one resistor for all seven segments: digit 1 would then pass the whole current through two LEDs and glow far brighter than 8, which shares it among seven.

• Common cathode: the shared pin goes to ground, segments are driven high. Use the 7448 or CD4511, or the equations above directly.
• Common anode: the shared pin goes to supply, segments are driven low. The 7447 has open-collector outputs that sink up to 40 mA and tolerate 15 V, so it can also drive larger lamps.
• Multiplexing: a four-digit module shares one decoder and enables one digit at a time. At 1/4 duty you need about four times the peak current for the same brightness, and a scan rate of 200 Hz or more per frame avoids visible flicker.
• Blanking: the 7447 and 7448 have lamp test, blanking and ripple-blanking pins to suppress leading zeros, so 0042 shows as 42.

Key fact: when the decoder and the display polarity disagree, every segment is inverted, so you see the complement of the digit. If an 8 looks blank and a blank looks like 8, swap polarity first and debug logic second.

Interview traps and extensions

Expect questions such as: how many product terms in total, what happens for input 1011, and how would you display hexadecimal. In a 7447, inputs 10 to 15 produce odd glyphs, while the CD4511 blanks them. To show A to F you extend the table to all 16 rows and lose the don’t-cares, so the equations grow. Another favourite is the ROM view: sixteen locations of seven bits, the textbook alternative to gates. If you want hands-on practice with Verilog and gate-level synthesis, our seven-segment display driver walkthrough continues from here, and the structured path lives on the CourseTron courses page. For hardware-focused VLSI training in India, ChipXpert’s VLSI training programmes take the same ideas into full ASIC flows.

Ready to go from K-maps to synthesised RTL? Join the CourseTron Digital Electronics course and build, simulate and verify your own decoder end to end.

Frequently asked questions

Why are inputs 10 to 15 don’t-cares?

A valid BCD digit never exceeds 1001. Since those six codes cannot occur, the designer may map them to anything, which lets K-map groups grow larger and the logic shrink.

What is the difference between 7447 and 7448?

The 7447 has active-low open-collector outputs for common-anode displays. The 7448 has active-high outputs with internal pull-ups for common-cathode displays.

How many gates does a BCD to 7-segment decoder need?

With the minimised equations above and shared product terms, roughly 20 to 25 two-level gates plus four inverters, depending on the library and how aggressively terms are shared.

Why do segment resistors matter?

Each LED needs its own current limit. Without it the current is set only by the forward-voltage mismatch and the driver, risking burnout and uneven brightness.