In short: The dft flow is the sequence of design-for-test steps that make a manufactured chip testable: inserting scan chains, generating test patterns with ATPG, compressing them to cut tester time, and signing off on fault coverage. It turns a functional netlist into one a tester can prove is defect-free.
The dft flow (Design-for-Test flow) is the structured set of steps engineers follow to add testability hardware to a chip and then generate the patterns that screen for manufacturing defects. A fabricated die can be functionally correct by design yet still carry physical faults — a bridged metal line, an open via, a stuck transistor — introduced during lithography, etch, or packaging. The dft flow exists to catch those parts before they reach a customer.
Rather than relying on functional vectors (which are slow to write and give poor coverage of internal nodes), the dft flow restructures the sequential logic so that automated tools can observe and control every flip-flop directly. The result is measured as fault coverage: the percentage of modeled faults a test set can detect. Modern digital blocks target 98–99%+ stuck-at coverage, with additional at-speed patterns for timing-related defects.
Without DFT, a tester can only drive primary inputs and watch primary outputs. Deep internal state is effectively unobservable, so defect escapes rise and test development becomes guesswork. The dft flow solves two problems at once: controllability (setting any internal node to a known value) and observability (reading any internal node back out). It also lowers test cost, because automatic pattern generation and compression slash the number of cycles each part spends on an expensive ATE (automatic test equipment) machine.
Economically, test can be 5–15% of the cost of a chip. A well-engineered dft flow with high compression ratios and tidy clocking directly reduces that bill while improving outgoing quality (measured in DPPM — defective parts per million).
Ordinary flip-flops are swapped for scan flip-flops that include a mux on the data input. A dedicated scan enable signal selects between normal (functional) data and a scan in path. The scan flops are then stitched into one or more scan chains — long shift registers that let the tester shift an arbitrary state into every flop and shift the captured response back out. This conversion happens on the gate-level netlist, typically right after synthesis, and tools re-check that functional timing is preserved.
With scan in place, an ATPG engine builds test vectors. For each modeled fault it solves two sub-problems: activation (drive the faulty node to the opposite of its stuck value) and propagation (create a sensitized path so the fault effect reaches an observable scan flop or output). Each pattern is a shift-in, one or more capture pulses, then shift-out. Algorithms such as PODEM and FAN, plus modern SAT-based solvers, make this tractable for millions of gates.
Raw scan data volume explodes with gate count, so an on-chip compression structure is inserted between the few tester pins and the many internal chains. A decompressor (often a ring generator / spreader network) fans a small stimulus into hundreds of short internal chains, and a compactor (typically an XOR-tree MISR or spatial compactor) folds the responses back down. Compression ratios of 50×–200× are common, cutting both test data volume and test time dramatically.
Finally the pattern set is graded: the tools report coverage per fault model, list undetected and untestable faults, and flag any patterns that violate DRC (design rule checks for test, such as uncontrolled clocks or bus contention). Patterns are simulated against the netlist — and often back-annotated with SDF for at-speed checks — before being written out in STIL or WGL format for the tester.
The dft flow rarely uses scan alone. A production chip combines several test methods, each targeting a different part of the die:
On the fault-model axis, the flow produces separate pattern sets for stuck-at, transition (at-speed), path-delay, and increasingly cell-aware and bridging faults as nodes shrink and defect behavior grows subtler.
Commercial EDA suites automate most of the flow. Synopsys DFTMAX / TestMAX (formerly TetraMAX), Siemens EDA Tessent, and Cadence Modus perform scan insertion, ATPG, and compression, and read the design constraints that keep test logic clean. A typical engineer-facing flow looks like this:
Teaching labs reproduce this with open PDKs (for example Nangate/FreePDK45) so students can stitch real chains, run ATPG, and read genuine coverage reports rather than just studying slides.
Real projects and industry tool flows, with certification.
Explore CourseTron Courses →Functional vectors reach very few internal nodes and are laborious to author, so coverage is low and unpredictable. Scan flops give the tester direct control and observation of every state element, letting ATPG achieve 98%+ fault coverage automatically. It trades a small area and a scan-enable pin for enormous testability gains.
Stuck-at patterns detect a node permanently held at 0 or 1 and need only one capture cycle, so they are generated at a slow shift clock. Transition (at-speed) patterns detect slow-to-rise/slow-to-fall defects and require two launch-capture pulses at functional frequency, typically using launch-off-capture or launch-off-shift schemes.
The decompressor expands a small amount of tester data into many short internal chains, and the compactor folds the responses back to few output pins. Because ATPG fills only the "care" bits and leaves the rest as don't-cares, the same faults stay detectable while test data volume and shift time drop by one to two orders of magnitude.
These are faults ATPG cannot detect because of redundancy, uncontrollable clocks/resets, or tied logic — not because the test set is weak. The right response is to confirm the cause: true redundant faults are excused from the coverage denominator, while DRC-blocked faults are fixed by cleaning up the test clocking or constraints and re-running.
Related: Memory BIST (MBIST) · the VLSI Glossary · all courses.