Courses

RISC-V Architecture & Design

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Design a complete RISC-V processor from scratch. Covers RISC-V ISA (RV32I/RV64I), 5-stage pipeline design, hazard detection, memory subsystem, interrupt handling, and SoC integration. Final project synthesises a full RISC-V core on FPGA and targets a standard cell library for ASIC tape-out.

Memory Compiler Design

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Understand memory compiler design and integration for ASIC chips. Covers SRAM architecture, memory compiler configuration, timing model interpretation, wrapper RTL design, memory BIST integration, and memory redundancy. Hands-on use of ARM Memory Compiler and Cadence Genus memory integration flows.

Constraint-Driven Design

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Learn how constraints drive RTL synthesis and physical design closure. Covers full SDC constraint creation, false path and multi-cycle path identification, clock definitions, I/O delay constraints, and constraint validation. Bridges the gap between RTL design and Physical Design handoff – a critical

Advanced FIFO Design

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Master FIFO design for synchronous and asynchronous clock domains. Covers FIFO depth estimation, pointer arithmetic, Gray code CDC FIFOs, almost-full/empty flags, burst-mode FIFOs, and synthesis-safe implementation. Includes formal verification of CDC properties and integration into AXI streaming in

RTL Design Course

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Learn professional RTL design methodology for ASIC chips. Covers microarchitecture planning, pipeline design, arbitration logic, CDC-awareness, lint-clean RTL, synthesis optimisation, and design-for-verification practices. Projects include designing a complete AXI-based SoC subsystem block.

Verilog

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Become proficient in Verilog for ASIC and FPGA design. Covers all Verilog constructs, synthesis-aware RTL coding, parameterisation, always blocks, generate statements, and testbench writing. Projects design arithmetic units, FIFOs, and state machines targeting real synthesis with Synopsys DC and Cad

Hardware Description Languages Basics

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Start your RTL journey with Hardware Description Languages. Introduces Verilog and VHDL syntax, module hierarchy, data types, concurrent vs sequential statements, simulation basics, and synthesis-friendly coding styles. Perfect for ECE graduates and IT professionals transitioning into VLSI/semicondu

Timing Closure & Optimization

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Learn systematic timing closure methodology for complex ASIC designs. Covers setup and hold ECOs, buffer/inverter insertion, cell sizing, clock skew exploitation, useful skew, and multi-corner timing closure strategies. Includes real ECO sessions on industrial-grade designs with 1000+ violations acr

Advanced STA Concepts

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Go beyond basic STA with advanced timing analysis. Covers AOCV/POCV statistical timing, CCSN/ECSM cell models, MMMC setup, advanced clock network analysis, hold margin management at advanced nodes, and ECO-driven timing closure. Essential for STA engineers working at 7nm and below.