Courses
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Learn Static Timing Analysis (STA) with full theory and practical lab sessions. Covers timing paths, setup/hold violations, clock skew, SDC constraints, multi-cycle paths, false paths, and timing closure methodology. Practical sessions use Cadence Tempus and Synopsys PrimeTime with real design datab
30 Lessons
15:17:39 Hours
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Learn Static Timing Analysis (STA) theory comprehensively. Covers timing paths, setup/hold violations, clock domain concepts, SDC constraints, multi-cycle paths, false paths, and timing closure theory. Provides the strong STA foundation needed before practical tool sessions with Cadence Tempus or Sy
30 Lessons
15:17:39 Hours
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The definitive end-to-end Physical Design course covering synthesis, floorplanning, power planning, placement, CTS, routing, signoff, and DRC/LVS. Uses Cadence Genus, Innovus, and Tempus on 14nm technology. Designed for engineers targeting PD roles at ASIC companies, fabless startups, and semiconduc
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Achieve timing signoff using Cadence Tempus with full theory and practical labs. Learn MCMM analysis, OCV/POCV, parasitic back-annotation, hold and setup fixing, and ECO flows. Directly applicable to tape-out flows in leading semiconductor companies with hands-on lab sessions on real design database
0 Lessons
Hours
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Learn timing signoff theory and methodology for ASIC tape-out. Covers multi-corner multi-mode (MCMM) analysis concepts, on-chip variation (OCV/POCV), parasitic back-annotation theory, and ECO flow fundamentals. Essential foundation before the Cadence Tempus practical signoff course.
0 Lessons
Hours
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Master the full Place and Route (PnR) flow using Cadence Innovus with theory and practical sessions. Covers design import, floorplanning, power planning, placement, CTS, routing, and post-route optimisation. Lab sessions use real 28nm/14nm standard cell libraries for hands-on industry-standard PD ex
25 Lessons
11:41:58 Hours
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Learn the complete Place and Route (PnR) flow theory for ASIC Physical Design. Covers design import, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and post-route optimisation concepts. Essential theory foundation before the Cadence Innovus practical course.
25 Lessons
11:41:58 Hours
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Master VLSI logic synthesis from RTL to gate-level netlist using Cadence Genus with full theory and practical labs. Covers synthesis flow setup, SDC constraint writing, timing and area optimisation, technology mapping, and QoR analysis. Hands-on sessions use real standard cell libraries at 28nm/14nm
14 Lessons
07:23:41 Hours
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Learn VLSI logic synthesis theory covering the RTL-to-gate-level netlist flow. Covers synthesis fundamentals, technology mapping theory, design constraint concepts, SDC syntax, and QoR metrics. Prerequisite to the Cadence Genus practical course. Ideal for engineers entering Physical Design who need
14 Lessons
07:23:41 Hours