Available now · Self-paced

Learn power integrity through EMIR analysis with theory and practical labs. Covers static and dynamic IR drop, electromigration violations, power grid debugging, decap insertion, and fixes using Cadence Voltus and Synopsys RedHawk. Labs use real power intent (UPF) and multi-power domain designs.

Available now · Self-paced

Learn EMIR (Electromigration and IR Drop) analysis theory for power integrity sign-off. Covers static and dynamic IR drop concepts, electromigration failure mechanisms, power grid analysis theory, decap insertion strategies, and EM/IR violation interpretation. Foundation before the Cadence Voltus/Re

Curriculum in preparation

Ensure your design is fabrication-ready through Physical Verification with theory and practical labs using Mentor Calibre. Covers DRC, LVS, ERC, and antenna checks. Learn foundry rule deck interpretation, violation debugging, and waiver flows essential for tape-out sign-off in any technology node.

Available now · Self-paced

Learn Physical Verification theory covering DRC (Design Rule Check), LVS (Layout vs Schematic), ERC, and antenna checks. Learn foundry rule deck interpretation, violation categories, and waiver methodology. Foundation course before the Mentor Calibre practical sessions. Essential for any engineer ta

Available now · Self-paced

Learn Static Timing Analysis (STA) with full theory and practical lab sessions. Covers timing paths, setup/hold violations, clock skew, SDC constraints, multi-cycle paths, false paths, and timing closure methodology. Practical sessions use Cadence Tempus and Synopsys PrimeTime with real design datab

Available now · Self-paced

Learn Static Timing Analysis (STA) theory comprehensively. Covers timing paths, setup/hold violations, clock domain concepts, SDC constraints, multi-cycle paths, false paths, and timing closure theory. Provides the strong STA foundation needed before practical tool sessions with Cadence Tempus or Sy

Curriculum in preparation

The definitive end-to-end Physical Design course covering synthesis, floorplanning, power planning, placement, CTS, routing, signoff, and DRC/LVS. Uses Cadence Genus, Innovus, and Tempus on 14nm technology. Designed for engineers targeting PD roles at ASIC companies, fabless startups, and semiconduc

Curriculum in preparation

Achieve timing signoff using Cadence Tempus with full theory and practical labs. Learn MCMM analysis, OCV/POCV, parasitic back-annotation, hold and setup fixing, and ECO flows. Directly applicable to tape-out flows in leading semiconductor companies with hands-on lab sessions on real design database

Curriculum in preparation

Learn timing signoff theory and methodology for ASIC tape-out. Covers multi-corner multi-mode (MCMM) analysis concepts, on-chip variation (OCV/POCV), parasitic back-annotation theory, and ECO flow fundamentals. Essential foundation before the Cadence Tempus practical signoff course.