Available now · Self-paced

Master the full Place and Route (PnR) flow using Cadence Innovus with theory and practical sessions. Covers design import, floorplanning, power planning, placement, CTS, routing, and post-route optimisation. Lab sessions use real 28nm/14nm standard cell libraries for hands-on industry-standard PD ex

Available now · Self-paced

Learn the complete Place and Route (PnR) flow theory for ASIC Physical Design. Covers design import, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and post-route optimisation concepts. Essential theory foundation before the Cadence Innovus practical course.

Available now · Self-paced

Master VLSI logic synthesis from RTL to gate-level netlist using Cadence Genus with full theory and practical labs. Covers synthesis flow setup, SDC constraint writing, timing and area optimisation, technology mapping, and QoR analysis. Hands-on sessions use real standard cell libraries at 28nm/14nm

Available now · Self-paced

Learn VLSI logic synthesis theory covering the RTL-to-gate-level netlist flow. Covers synthesis fundamentals, technology mapping theory, design constraint concepts, SDC syntax, and QoR metrics. Prerequisite to the Cadence Genus practical course. Ideal for engineers entering Physical Design who need

Curriculum in preparation

Understand processor internals through Assembly Language programming. Covers ISA, ARM and RISC-V assembly syntax, memory addressing modes, subroutines, interrupt handling, and interfacing with C code. Critical for embedded hardware engineers, RISC-V SoC developers, and anyone targeting processor des

Curriculum in preparation

Learn GIT version control tailored for hardware and VLSI engineers. Covers repository setup, branching, merging, tagging RTL releases, resolving conflicts, and integration with EDA tool flows. Essential for team-based VLSI projects across Physical Design, RTL, and Verification teams.

Curriculum in preparation

Understand the intersection of embedded systems and VLSI design. Covers microcontroller architecture, hardware/software co-design, peripheral interfaces (UART, SPI, I2C), memory maps, and bare-metal programming. Designed for engineers targeting SoC, FPGA, or embedded hardware roles in the semiconduc

Available now · Self-paced

Learn TCL – the native scripting language of most EDA tools. Covers TCL fundamentals, procedures, control flow, and direct application within Cadence Innovus, Synopsys DC, and Tempus. Write real design flow scripts, custom constraints, and automated ECO flows used in production Physical Design envir

Curriculum in preparation

Master Perl scripting for VLSI and EDA automation. Covers Perl syntax, regular expressions, file handling, hash/array manipulation, and scripting for Cadence Innovus, Synopsys DC, and Tempus. Learn log parsers, timing violation scripts, and QoR report automation tools used daily by Physical Design e