Courses
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Analyse and fix signal and power integrity issues in high-speed VLSI designs. Covers crosstalk noise, glitch analysis, transmission line effects, aggressor-victim coupling, SI-driven routing rules, and co-simulation of SI/PI using Cadence Sigrity and Innovus SI flows.
0 Lessons
Hours
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Design robust Power Delivery Networks (PDN) for high-performance ICs. Covers PDN impedance analysis, power mesh design, decoupling capacitor placement, bump assignment for flip-chip designs, and PDN simulation using Cadence Voltus. Includes advanced topics on package-chip co-design and chiplet PDN c
0 Lessons
Hours
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Tackle advanced routing challenges in modern ASIC designs. Covers global and detail routing algorithms, congestion analysis and mitigation, DRC-clean routing strategies, shield routing for sensitive nets, and post-route ECOs. Project-based course using Cadence Innovus Nanoroute on a real hierarchica
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Hours
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Design power-efficient ICs with advanced low-power techniques. Covers clock gating, power gating, multi-voltage domain design, UPF/CPF power intent, DVFS strategies, retention flops, isolation cells, and level shifters. Essential for engineers working on mobile SoCs, automotive ICs, and IoT chip des
0 Lessons
Hours
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Master floorplanning and chip-level planning for ASIC design. Learn die size estimation, aspect ratio selection, macro placement strategies, power ring and stripe design, IO planning, and hierarchical floorplanning techniques. Uses Cadence Innovus with real SoC hierarchical designs for practical ses
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Hours
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Learn power integrity through EMIR analysis with theory and practical labs. Covers static and dynamic IR drop, electromigration violations, power grid debugging, decap insertion, and fixes using Cadence Voltus and Synopsys RedHawk. Labs use real power intent (UPF) and multi-power domain designs.
3 Lessons
01:28:54 Hours
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Learn EMIR (Electromigration and IR Drop) analysis theory for power integrity sign-off. Covers static and dynamic IR drop concepts, electromigration failure mechanisms, power grid analysis theory, decap insertion strategies, and EM/IR violation interpretation. Foundation before the Cadence Voltus/Re
9 Lessons
05:08:10 Hours
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Ensure your design is fabrication-ready through Physical Verification with theory and practical labs using Mentor Calibre. Covers DRC, LVS, ERC, and antenna checks. Learn foundry rule deck interpretation, violation debugging, and waiver flows essential for tape-out sign-off in any technology node.
0 Lessons
Hours
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Learn Physical Verification theory covering DRC (Design Rule Check), LVS (Layout vs Schematic), ERC, and antenna checks. Learn foundry rule deck interpretation, violation categories, and waiver methodology. Foundation course before the Mentor Calibre practical sessions. Essential for any engineer ta
11 Lessons
08:17:01 Hours