Courses

Analog Custom Layout Courses

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Advanced custom layout techniques for high-performance analog and RF ICs. Covers RF layout for inductors and capacitors, deep submicron layout challenges, FinFET layout rules, advanced matching, thermal considerations, and tape-out preparation for 28nm/16nm technology nodes using Cadence Virtuoso.

Analog Mixed Signal Design

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Master Analog/Mixed-Signal (AMS) design for SoC integration. Covers ADC and DAC architectures, PLL design and analysis, bandgap references, LDO regulators, and analog-digital interface challenges. AMS co-simulation using Cadence Virtuoso AMS with Verilog-A models bridges the gap between analog and d

Analog Circuit Design

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Design CMOS analog circuits from first principles using Cadence Spectre. Covers biasing, current mirrors, differential pairs, single-stage and multi-stage amplifiers, op-amp design, bandwidth, stability, and noise analysis. Simulation on real technology PDKs. Essential for analog IC designers and mi

Analog Layout Design

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Learn professional analog IC layout techniques using Cadence Virtuoso. Covers MOSFET layout, matching techniques, common centroid structures, guard rings, shielding, ESD protection layout, DRC/LVS clean design, and parasitic-aware layout optimisation. Targeted at engineers seeking analog, mixed-sign

Formal Verification

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Apply formal verification to prove design correctness mathematically. Covers SVA property writing, model checking theory, assume-guarantee reasoning, and tool-driven formal apps (connectivity, CDC, datapath) using Cadence JasperGold and Synopsys VC Formal. Real sign-off projects on bus interface and

Clock Domain Crossing (CDC) Training

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Master CDC analysis and verification. Covers metastability, synchroniser design, multi-bit CDC paths, gray code FIFOs, CDC waivers, and formal CDC sign-off using SpyGlass and Mentor Questa CDC. Critical for SoC designs with multiple clock domains – a leading cause of silicon bugs.

Testbench Development

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Learn structured testbench development for VLSI designs. Covers testbench architecture, stimulus generation, self-checking testbenches, assertion-based verification, functional coverage planning, and verification closure methodology. Uses Synopsys VCS and Cadence Xcelium simulators with real ASIC de

UVM

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Master UVM – the industry-standard ASIC verification methodology. Build a complete UVM testbench from scratch: agents, drivers, monitors, scoreboards, coverage collectors, and virtual sequences. Covers RAL, callback hooks, factory overrides, and coverage closure. Projects target AXI and PCIe protoco

System Verilog

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Learn SystemVerilog for design verification with OOP methodology. Covers SV data types, interfaces, clocking blocks, SVA assertions, functional coverage, and constraint-random stimulus. Essential prerequisite for UVM and used across all ASIC verification teams globally.