Courses

PCIe Gen4 Training

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Learn PCIe Gen4 protocol architecture and verification. Covers PCIe layered architecture, Gen4 electrical specifications, LTSSM link training, TLP/DLLP packet structures, flow control, and PCIe Gen4 DV methodology using SystemVerilog and UVM-based PCIe VIP.

Design and Verification Course

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The complete package for engineers targeting both Design and Verification roles. Covers Verilog RTL design, SystemVerilog, UVM testbench construction, simulation-based verification, and synthesis handoff. Designed for final-year students and career-switchers seeking full-stack VLSI competency with a

BIST – Memory & Logic

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Design and implement BIST structures for memories and logic. Covers MBIST controller design, March test algorithms, memory repair, LBIST architectures, LFSR pattern generators, MISR compactors, and at-speed BIST for automotive ISO 26262 requirements. Uses Mentor Tessent MBIST flow.

ATPG & Test Pattern Generation

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Generate high-quality test patterns using ATPG for maximum fault coverage. Covers stuck-at, transition, and path delay fault models, fault simulation, ATPG pattern optimisation, diagnostic patterns, and tester-ready pattern export. Uses Synopsys TetraMAX and Mentor Tessent on real SoC designs.

Scan Chain Insertion & Compression

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Master scan chain design and test compression. Covers scan flip-flop selection, scan enable routing, EDT/OPMISR compression, scan reordering, X-bounding, and test data volume reduction. Hands-on with Synopsys DFT Compiler and Mentor Tessent for real ASIC scan insertion and ATPG pattern generation.

Design for Testability (DFT)

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Learn the fundamentals of DFT for ASIC and SoC designs. Covers stuck-at and transition fault models, scan chain insertion, test compression (EDT), boundary scan (JTAG/IEEE 1149.1), ATPG fundamentals, and DFT sign-off methodology. Uses Synopsys DFT Compiler and Mentor Tessent flows.

Power Management IC (PMIC) Design

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Design complete Power Management ICs (PMIC). Covers LDO regulator design, buck and boost DC-DC converter architectures, bandgap references, charge pumps, battery management circuits, and multi-rail PMIC integration. Design and simulate complete PMIC blocks using Cadence Virtuoso with automotive and

RF/Analog Co-Design

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Design RF circuits in standard CMOS technology. Covers LNA, mixer, VCO, and PA design; S-parameter analysis; noise figure optimisation; impedance matching; and RF layout strategies. Uses Cadence Virtuoso with RF PDKs for simulation and layout. Targeted at wireless SoC, IoT, and RF IC design engineer

I/O Design & High-Speed Serial Interfaces

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Design robust I/O pads and high-speed serial interfaces for modern SoCs. Covers ESD protection circuits, IO pad design, SERDES architecture, LVDS/differential signalling, DDR IO training circuits, and impedance-controlled IO using IBIS models and ADS simulation.