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Learn the DisplayPort protocol for high-resolution display interfaces. Covers DP 1.4 and DP 2.0 (UHBR) architecture, main link and AUX channel, link training, MST, HDCP 2.3, DSC, and USB-C integration. Targeted at multimedia SoC and GPU design engineers.
0 Lessons
Hours
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Learn UART – the most fundamental serial communication protocol. Covers UART framing (start/stop/parity bits), baud rate generation, RS232/RS485 levels, FIFO-buffered UART design, flow control (RTS/CTS), and UART controller RTL implementation.
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Hours
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Master the I2C protocol for sensor and peripheral interfaces. Covers I2C multi-master arbitration, clock stretching, 10-bit addressing, SMBus extensions, I2C timing analysis, and I2C controller RTL implementation with bus contention and NAK scenario testing.
32 Lessons
16:05:01 Hours
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Learn the SPI protocol for embedded and SoC design. Covers SPI modes (CPOL/CPHA), master/slave architecture, full-duplex transfers, multi-slave topologies, Quad-SPI (QSPI) for NOR flash, and SPI controller RTL design with UVM SPI VIP verification.
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Hours
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Learn USB4 – the convergence of USB and Thunderbolt 3 at 40Gbps. Covers USB4 tunnelling architecture (USB 3.2, DisplayPort, PCIe tunnels), bandwidth management, USB4 hub topology, power delivery 3.0, and backwards compatibility.
0 Lessons
Hours
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Deep-dive into USB 3.x SuperSpeed protocol from USB 3.0 to USB 3.2 Gen2x2. Covers LFPS, link training, USB 3.x packet structure, power management (U0-U3 states), USB-C integration, and dual-role power delivery with UVM VIP verification.
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Hours
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Learn USB 2.0 protocol architecture for SoC integration and verification. Covers USB host/device/OTG architecture, full-speed/high-speed specs, enumeration sequence, USB packet types, USB controller design, ULPI PHY interface, and DV methodology using UVM USB VIP.
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Hours
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Master LPDDR5 and LPDDR5X for mobile and IoT SoC designs. Covers WCK architecture, link-ECC, deep power down modes, DVFSC, and differences from DDR5. Critical for engineers designing memory subsystems in smartphone, automotive, and wearable SoC applications.
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Hours
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Advance to DDR5 – the latest DRAM standard with doubled bandwidth and on-die ECC. Covers DDR5 channel architecture, decision feedback equalisation (DFE), on-die ECC, DDR5 PMIC integration, CA parity, and DDR5 controller/PHY design considerations.
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Hours