Curriculum in preparation

Bridge RTL design with FPGA implementation. Covers FPGA-specific RTL coding styles, resource-aware synthesis, mapping to BRAM/DSP primitives, timing closure methodology, and FPGA-to-ASIC migration. Projects implement AXI-connected signal processing blocks on Xilinx UltraScale FPGA hardware.

Curriculum in preparation

Learn the end-to-end FPGA design flow using Xilinx Vivado and Intel Quartus Prime. Covers RTL simulation, synthesis, technology mapping, placement, routing, timing constraint entry, bitstream generation, and in-system debug (ILA/SignalTap) on real Xilinx Artix-7 and Intel Cyclone V boards.

Available now · Self-paced

Start your FPGA journey with a comprehensive look at FPGA architecture and fundamentals. Covers CLBs, LUTs, flip-flops, BRAM, DSP blocks, clock resources, and IO banks for Xilinx UltraScale+ and Intel Agilex FPGAs. Ideal for ECE graduates and software engineers transitioning into FPGA roles.

Curriculum in preparation

Validate power and thermal performance of silicon chips. Covers TDP measurement, IDD current profiling, thermal resistance measurement, die temperature mapping, thermal throttling validation, DVFS characterisation, and power-state sequence verification using real power analysis boards and thermal ca

Curriculum in preparation

Learn systematic Failure Analysis (FA) and root cause debugging for silicon defects. Covers FA workflow, SEM, FIB cross-section, OBIC, photoemission microscopy, and backside debug. Bridges validation findings with wafer-level defect analysis for yield and reliability improvement.

Curriculum in preparation

Characterise silicon performance across PVT (Process, Voltage, Temperature) corners. Covers V/F shmoo plots, speed binning, leakage and active power measurement, PVT sensitivity analysis, and statistical data analysis for characterisation report generation.

Curriculum in preparation

Master oscilloscope and logic analyser use for chip bring-up and debug. Covers probing techniques, bandwidth and sample rate selection, triggering, waveform analysis, logic analyser state/timing modes, protocol decoding (I2C, SPI, UART), and mixed-signal debug using Keysight and Tektronix equipment.

Curriculum in preparation

Debug high-speed IOs (PCIe, DDR, USB) on real silicon. Covers eye diagram measurements, BER testing with BERT, protocol analyser usage, DDR training algorithm debug, PCIe link training failure analysis, and USB enumeration debug using real silicon boards and instruments.

Curriculum in preparation

Learn systematic silicon bring-up and debug methodology for first-silicon success. Covers power-up sequence validation, clock and reset bring-up, JTAG access, basic register reads, memory test, and boot flow debugging. Includes real case studies of silicon bring-up challenges and fault isolation tec