Courses

Failure Analysis and Root Cause Debug

Buy now

Learn systematic Failure Analysis (FA) and root cause debugging for silicon defects. Covers FA workflow, SEM, FIB cross-section, OBIC, photoemission microscopy, and backside debug. Bridges validation findings with wafer-level defect analysis for yield and reliability improvement.

Silicon Characterisation and Coverage

Buy now

Characterise silicon performance across PVT (Process, Voltage, Temperature) corners. Covers V/F shmoo plots, speed binning, leakage and active power measurement, PVT sensitivity analysis, and statistical data analysis for characterisation report generation.

Oscilloscope and Logic Analyser for Chips

Buy now

Master oscilloscope and logic analyser use for chip bring-up and debug. Covers probing techniques, bandwidth and sample rate selection, triggering, waveform analysis, logic analyser state/timing modes, protocol decoding (I2C, SPI, UART), and mixed-signal debug using Keysight and Tektronix equipment.

High-Speed IO Debug PCIe DDR USB

Buy now

Debug high-speed IOs (PCIe, DDR, USB) on real silicon. Covers eye diagram measurements, BER testing with BERT, protocol analyser usage, DDR training algorithm debug, PCIe link training failure analysis, and USB enumeration debug using real silicon boards and instruments.

Lab Bring-Up and Debug Methodology

Buy now

Learn systematic silicon bring-up and debug methodology for first-silicon success. Covers power-up sequence validation, clock and reset bring-up, JTAG access, basic register reads, memory test, and boot flow debugging. Includes real case studies of silicon bring-up challenges and fault isolation tec

Post Silicon Validation Fundamentals

Buy now

Introduction to post-silicon validation for new chip bring-up and characterisation. Covers validation planning, lab setup, DUT bring-up sequence, basic measurements, debug tool selection, and validation-to-spec methodology. Designed for graduates and firmware engineers transitioning into silicon val

Advanced Packaging Wafer Level and 3D-IC

Buy now

Learn advanced IC packaging technologies driving the chiplet era. Covers WLP, FOWLP, TSV, 2.5D interposer (CoWoS), 3D stacking, SiP, and thermal/mechanical design for advanced packages. Essential for engineers working on AI, HPC, and mobile SoC packaging roadmaps.

Yield Analysis and Defect Engineering

Buy now

Improve chip yield through systematic defect engineering and yield analysis. Covers Poisson and negative binomial yield models, defect density measurement, inline inspection (SEM/optical), wafer map analysis, defect-limited vs parametric yield, and DFM impact on yield.

Device Characterisation and Modelling

Buy now

Learn transistor device characterisation and SPICE model extraction. Covers DC/AC measurement techniques, Id-Vg and Id-Vd characterisation, BSIM4/BSIM-CMG model parameters, process corner definition, Monte Carlo variation modelling, and PDK model card creation.