Courses

Lithography Fundamentals and EUV

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Understand modern lithography technology driving sub-7nm patterning. Covers optical lithography fundamentals, DUV immersion lithography, EUV technology, OPC and mask data preparation, multiple patterning (SADP/SAQP), and stochastic effects at advanced nodes.

Back-End-of-Line BEOL and Interconnects

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Learn BEOL interconnect fabrication for modern ICs. Covers copper dual-damascene process, barrier layers, low-k dielectric materials, via and metal formation, CMP, RC delay modelling, and electromigration reliability. Essential for Physical Design engineers who need to understand the fabrication bas

CMOS Fabrication Process Front-End

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Deep-dive into CMOS Front-End-of-Line (FEOL) fabrication. Covers wafer preparation, thermal oxidation, diffusion and ion implantation, photolithography patterning, etching, CVD deposition, CMP, and MOSFET formation with impact on device electrical characteristics.

Semiconductor Process Technology Overview

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Understand semiconductor manufacturing process technology from 180nm to sub-5nm nodes. Covers CMOS scaling trends, Moore's Law, front-end and back-end processes, technology node definitions, foundry vs IDM, and the impact of process technology on design rules.

ATE Training

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Learn ATE operation and test program development for semiconductor production test. Covers ATE system architecture (Advantest/Teradyne), device interface boards (DIB/load board), test program creation, parametric and functional test, yield improvement through ATE data analysis, and ATE-DFT co-design

UCIe Protocol Training

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Learn UCIe – the open standard for chiplet-based die-to-die interconnects. Covers UCIe physical and protocol layers, die-to-die adapter architecture, advanced and standard packaging form factors, and UCIe IP integration strategy.

HBM3 Protocol Training

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Learn HBM3 – the ultra-high-bandwidth memory used in AI accelerators and GPUs. Covers HBM3 architecture, 3D stacking (TSV), wide 1024-bit interface, refresh management, thermal design, and HBM3 PHY interface. Essential for AI chips, GPUs, and network processors.

CXL Protocol Training

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Master CXL – the emerging coherent interconnect for CPU-accelerator-memory systems. Covers CXL 1.1/2.0/3.0 specifications, CXL.io, CXL.cache, CXL.mem, and CXL switch topology. Essential for AI accelerator, HPC, and data centre SoC engineers.

NVMe Training

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Learn NVMe (NVM Express) – the high-performance storage protocol over PCIe. Covers NVMe command set, submission/completion queue pairs, admin commands, NVMe namespaces, power management, and NVMe-oF with NVMe controller DV methodology.