Courses

DDR Training

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Learn DDR DRAM protocol from fundamentals to controller implementation. Covers DDR4 command/address bus, timing parameters (tCL, tRCD, tRP), read/write burst flows, power states, auto-refresh, and DDR PHY interface with UVM DDR VIP verification.

AMBA - ACE Protocol Training

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Learn AMBA ACE (AXI Coherency Extensions) for cache-coherent multi-processor SoCs. Covers snoop channels, barrier transactions, domain types, ACE-Lite for IO coherency, and integration with ARM CoreLink CCI and CCN interconnects.

AMBA - CHI Protocol Training

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Understand the AMBA CHI (Coherent Hub Interface) protocol for multi-core SoC cache coherency. Covers CHI network layers, transaction types (read, write, snoop), CHI-B and CHI-E specifications, QoS, and integration with ARM CoreLink interconnects.

AMBA - APB Protocol Training

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Learn the AMBA APB protocol for low-power SoC peripherals. Covers APB2 and APB3 transaction flows, PPROT security extensions, PSTRB byte strobes, APB bridge design, and peripheral register map implementation.

AMBA - AHB Protocol Training

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Master the AMBA AHB (Advanced High-performance Bus) protocol for SoC design. Covers AHB master/slave/arbiter architecture, transfer types, burst transactions, AHB-Lite simplification, and pipeline transfers used widely in microcontrollers and embedded SoCs.

AMBA - AXI Protocol Training

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Learn the AMBA AXI protocol – the backbone of modern SoC designs. Covers AXI4 read/write channels, handshaking, burst types, AXI-Lite for register access, AXI-Stream for data streaming, and AXI interconnect topology. Includes UVM-based AXI verification environment development for real SoC subsystems

PCIe Testbench (TB) Development Training

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Build a complete PCIe UVM testbench from scratch. Covers PCIe agent architecture, TLP/DLLP generation, link training sequences, error injection, protocol checkers, coverage models, and regression methodology targeting PCIe endpoint and root complex implementations.

PCIe Gen6 Training

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Prepare for PCIe Gen6 – the next-generation 64GT/s interconnect using PAM4 signalling. Covers Gen6 FLIT-based encoding, PAM4 vs NRZ, L0p power state, FEC in Gen6, and CXL 3.0 co-evolution. Ideal for engineers at the frontier of high-speed interconnect design.

PCIe Gen5 Training

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Deep-dive into PCIe Gen5 at 32GT/s. Covers Gen5 physical layer improvements, signal integrity challenges, equalization, FEC, PCIe 5.0 spec changes, and interaction with CXL 2.0. Targeted at DV and hardware engineers in data centre and AI accelerator companies.