Switched-capacitor circuits

In short: A switched-capacitor (SC) circuit uses a capacitor toggled between two nodes by non-overlapping clock phases to shuttle discrete packets of charge, which behaves like a resistor of value R = 1/(f_CLK·C) — letting analog designers build precise, programmable integrators, filters, and ADCs on a CMOS die where real resistors are large, inaccurate, and drifty.

The core trick: a capacitor plus a clock is a resistor

In a pure CMOS process you can pattern a capacitor to roughly 0.1 % matching, but a diffused or poly resistor varies ±20–30 % across process corners and drifts with temperature. That is a disaster for a filter whose cutoff depends on an absolute RC product. Switched-capacitor design sidesteps the problem entirely: instead of a physical resistor, you move charge in quantized lumps and let the clock set the "resistance".

Consider a capacitor C connected by two switches driven by non-overlapping phases φ1 and φ2. On φ1 the cap charges to node voltage V₁; on φ2 it dumps its charge onto V₂. The charge transferred per clock cycle is ΔQ = C(V₁−V₂). Repeating this f_CLK times per second gives an average current I = ΔQ·f_CLK = C·f_CLK·(V₁−V₂). By Ohm's law that is identical to a resistor of value R_eq = 1/(f_CLK·C).

A 1 pF capacitor clocked at 1 MHz emulates a 1 MΩ resistor — occupying a fraction of the silicon a real 1 MΩ poly resistor would demand, and tunable simply by changing the clock.

Watch the charge move

The animation below shows a single charge packet being picked up on φ1 and delivered on φ2 — the physical essence of SC operation. The two switches never close at the same time; that non-overlap guarantee prevents charge from leaking straight through.

The SC integrator — the workhorse block

Replace the input resistor of a classic op-amp integrator with an SC branch and you get a parasitic-insensitive SC integrator. Its transfer function is governed by the ratio of two capacitors, C_S (sampling) and C_I (integrating), not by an absolute RC. In the z-domain a non-inverting integrator looks like H(z) = (C_S/C_I)·z⁻¹/(1−z⁻¹). Because the gain depends only on a capacitor ratio, it inherits the 0.1 % matching of lithography rather than the 20 % tolerance of a resistor.

This is the single most important property of SC design: time constants are set by capacitor ratios and a crystal-accurate clock. A quartz oscillator holds f_CLK to a few ppm, so a filter corner that scales with f_CLK·(C_S/C_I) can be accurate to better than 1 %. Tools like Cadence Spectre and Synopsys HSPICE simulate these blocks with periodic steady-state (PSS) and pnoise analyses, which are built precisely for clocked, time-varying circuits.

Building filters and ADCs

Cascade SC integrators and you can realise any biquad. A second-order SC low-pass or bandpass is assembled from two integrators in a loop with a few ratioed feedback caps — the same topology as a Tow-Thomas active-RC filter but immune to absolute-value drift. Commercial anti-aliasing and smoothing filters, PGAs, and sigma-delta modulators lean on this.

The most consequential modern use is the sigma-delta (ΣΔ) ADC. Its loop filter is a chain of SC integrators; the 1-bit quantiser feeds charge back through an SC DAC. Oversampling plus noise shaping pushes quantisation noise out of band, yielding 16–24 effective bits for audio and instrumentation. The same SC front end also performs the sample-and-hold operation at the input — see our deep dive on the sample-and-hold circuit for how the acquisition and droop behave, and our note on op-amp slew rate for why the amplifier must settle within half a clock phase.

kT/C noise sets a hard floor: at room temperature a 1 pF sampling cap contributes ≈64 µV RMS of sampled noise. Halving noise voltage means quadrupling C — a direct area/power vs. resolution trade every SC designer negotiates.

The gotchas that bite in silicon

• Charge injection & clock feedthrough: when a MOS switch turns off, channel charge dumps onto the cap, creating offset and gain error. Dummy switches, bottom-plate sampling, and fully-differential topologies cancel most of it.
• Finite op-amp gain & bandwidth: the amplifier must settle to the target accuracy within half a clock period. At 10 MHz that is 50 ns — demanding gain-bandwidth well above 100 MHz for 12-bit settling.
• Aliasing: an SC circuit is a sampled system, so any input energy near multiples of f_CLK folds into the band. A continuous-time anti-alias filter in front is mandatory.
• Clock non-overlap: too little dead time shorts the branch; too much wastes settling budget. The phase generator is as carefully designed as the analog core.

Mastering these is exactly the skill set analog teams hire for. If you want structured, lab-based training on CMOS analog and mixed-signal design, ChipXpert's VLSI programs cover SC blocks end to end.

Ready to design your own SC integrator and sigma-delta loop in Cadence Virtuoso? The CourseTron Analog & Mixed-Signal course walks you from the charge-transfer equation to a tape-out-ready ADC front end.

Frequently asked questions

Why not just use a real resistor on-chip?

On-chip resistors are large, have ±20–30 % absolute tolerance, drift with temperature, and are hard to tune. A switched capacitor gives a resistance set by a precise clock and a well-matched cap ratio, in less area and fully programmable.

What sets the accuracy of an SC filter's cutoff frequency?

The product of the clock frequency and a capacitor ratio. Crystal clocks are accurate to ppm and cap ratios match to ~0.1 %, so the corner can be held to under 1 % — far better than any absolute-RC filter.

What is kT/C noise and why does it matter?

Each sampling event stores thermal noise of mean-square value kT/C on the capacitor. It sets the fundamental noise floor of an SC stage; the only way to lower it is to increase C, which costs area and power.

Do I need an anti-aliasing filter with an SC circuit?

Yes. Because an SC circuit samples at f_CLK, energy near multiples of the clock aliases into the signal band. A simple continuous-time RC filter at the input prevents this.