In short: A sample-and-hold (S/H) circuit freezes an analog voltage on a capacitor so an ADC can digitize a stationary value, and its accuracy is governed by how fast it can charge the cap (acquisition), how little it corrupts that value when the switch opens (charge injection / pedestal) and how little it leaks during conversion (droop).
Every data converter you will meet in an interview — pipeline, SAR, flash front-ends — depends on a sample-and-hold (often called a track-and-hold, T/H) to present a frozen sample to the quantizer. Without it, a fast-moving input would move during conversion and the code you read back would be meaningless. This article walks through the real circuit, the non-idealities that dominate silicon, and the numbers that matter.
The basic topology: switch + hold capacitor
The canonical S/H is deceptively simple: a MOS switch connects the input to a hold capacitor CH, and a unity-gain buffer reads the stored voltage without loading it. In track mode the switch is closed and VC follows VIN; in hold mode the switch opens and CH stores the last tracked value.
Sizing CH is the first real engineering trade-off. The sampled thermal noise is the famous kT/C: its RMS value is √(kT/CH). For CH = 1 pF at 300 K that is about 64 µV RMS. To get 12-bit SNR against a 1 VRMS signal you often need several picofarads; but a bigger cap is slower to charge and burns more power in the driver. This single equation is why 14-bit SAR ADCs use 2–10 pF sampling caps and why you cannot "just make it tiny."
kT/C noise is set only by the capacitor value, not by the switch resistance. The switch Ron sets the noise bandwidth, but the total integrated sampled noise stays √(kT/C). You buy SNR with capacitance.
Acquisition time — how fast can you track?
When the switch closes, CH charges through Ron with time constant τ = Ron·CH. To settle to 0.5 LSB of an N-bit converter you need roughly (N+1)·ln(2) time constants. For a 12-bit part that is about 9τ; for 14-bit, about 10.4τ. With Ron = 100 Ω and CH = 2 pF, τ = 200 ps, so 12-bit acquisition needs ≈1.8 ns — comfortable for a 100 MS/s converter but tight at GS/s rates, which is why designers push Ron down with wide switches or bootstrapping.
Charge injection and clock feedthrough — the pedestal error
Here is where interviews get interesting. A MOS switch holds channel charge Qch = W·L·Cox·(VGS−Vt) while it conducts. When the gate turns off, that charge has to go somewhere, and a fraction dumps onto CH, shifting the held voltage by a pedestal ΔV ≈ Qch/(2·CH). Simultaneously the gate-to-drain overlap capacitance couples the falling clock edge onto the node — clock feedthrough.
The nasty part: charge injection depends on VGS, which depends on the input signal, so the error is signal-dependent and shows up as harmonic distortion, not a benign offset. Classic mitigations you should be able to name:
- Dummy switch — a half-size device clocked out of phase absorbs roughly half the injected charge.
- Bottom-plate sampling — open a signal-independent switch (tied to ground/common-mode) first, so the charge injected is constant and cancels as common-mode. This is the single most important trick in modern SAR and pipeline front-ends.
- Bootstrapped (gate-boosted) switch — hold VGS constant at VDD regardless of input, linearizing Ron and making injection input-independent.
- Fully differential topology, so the pedestal appears as common-mode and is rejected.
Droop — leakage during hold
Once the switch is open, CH is not perfectly isolated. Subthreshold leakage through the off switch, buffer input bias current, and junction leakage all slowly discharge (or charge) the node. The droop rate is dV/dt = Ileak/CH. With 1 pA of leakage and 2 pF, that is 0.5 µV/µs — negligible for a 1 µs SAR conversion but significant if the hold time stretches, or at high temperature where leakage doubles roughly every 8–10 °C. Droop is why you keep the hold window short and favor CMOS buffers with fA-class gate leakage over bipolar buffers with nA base currents.
Putting the errors in one place
| Error | When | Scales with | Primary fix |
|---|---|---|---|
| kT/C noise | sampling | 1/√CH | larger CH |
| Acquisition / settling | track→valid | Ron·CH | wider / bootstrapped switch |
| Charge injection | switch opens | W·L·Cox/CH | bottom-plate, dummy, differential |
| Clock feedthrough | switch opens | Cov/CH | differential, small Cov |
| Droop | hold | Ileak/CH | low-leakage buffer, short hold |
| Aperture jitter | sampling instant | Δt·dV/dt | low-jitter clock |
Aperture jitter sets the ceiling for high-speed converters: SNRjitter = −20·log(2πfin·σt). For a 100 MHz input, holding 12-bit SNR (~74 dB) demands σt below ~300 fs of clock jitter.
Verifying it in a real flow
In practice you characterize all of this in SPICE. Engineers sweep the pedestal versus input in Cadence Spectre (a DC-then-transient "turn-off" testbench), run a PSS/PAC or long transient FFT to extract SFDR/THD, and check kT/C with .noise transient or periodic-noise (pnoise) analysis. Synopsys HSPICE and FineSim are common for sign-off accuracy, and layout parasitics from Siemens Calibre PEX are back-annotated because the real Cov and CH mismatch set the final distortion. The lesson students miss: the S/H almost always limits the converter's SFDR before the quantizer does.
If you are building toward tape-out skills, hands-on S/H design is one of the first analog blocks we cover in our analog track — and our sister brand Avecas design services uses the same bootstrapped-switch front-ends in production mixed-signal IP.
For the bigger picture of how the S/H feeds different quantizers, read our companion piece on ADC architectures, and for the switch-level device physics see MOS switch design. Both build directly on the concepts here.
Ready to design your own bootstrapped sample-and-hold and simulate it in Spectre? Join the CourseTron Analog & Data Converters track — browse all CourseTron courses →
Frequently asked questions
What is the difference between sample-and-hold and track-and-hold?
They are the same core circuit; the distinction is emphasis. A track-and-hold explicitly tracks (follows) the input continuously while the switch is closed, then holds. "Sample-and-hold" often implies a brief sampling instant. In modern CMOS data converters the terms are used interchangeably for the switch-plus-cap front-end.
Why does charge injection cause distortion rather than a simple offset?
The channel charge a MOS switch injects depends on its overdrive VGS−Vt, which moves with the input signal. Because the error is a function of the signal itself, it folds into harmonics (THD) instead of appearing as a constant, correctable offset.
How do I choose the hold capacitor value?
Start from the noise budget: pick CH large enough that √(kT/CH) is below your target LSB, then check that the driver can charge it within the acquisition window and that matching/area are acceptable. It is always a noise-versus-speed-versus-power triangle.
What limits sample-and-hold performance at high frequency?
Aperture jitter and incomplete settling dominate. Clock jitter directly adds noise proportional to the input slew rate, and if Ron·CH settling is too slow the held value lags the true input, both degrading SFDR and SNR.