In short: Every MOSFET is classified by two independent choices: whether a channel exists at zero gate voltage (depletion) or must be induced (enhancement), and whether the carriers are electrons (n-channel) or holes (p-channel), which gives four devices, of which the enhancement NMOS and enhancement PMOS make up virtually all modern CMOS.
Two questions decide the type
Ask any interviewer to "list the types of MOSFET" and the weak answer is a memorised list of four names. The strong answer starts from two yes/no questions you can ask of any transistor. First, with the gate tied to the source (VGS = 0), is there already a conducting channel? Second, is the current carried by electrons or by holes? The first question separates enhancement from depletion; the second separates n-channel from p-channel. Four combinations follow, and each one has a predictable sign for its threshold voltage. If you have not yet seen how the inversion layer forms under the oxide, read how a MOSFET works first, because everything below builds on that picture.
Enhancement versus depletion
An enhancement-mode device is normally OFF. The body under the gate is the opposite doping type from source and drain, so with VGS = 0 the two junctions are back-to-back diodes and only leakage flows. You must push the gate beyond the threshold voltage Vth to "enhance" a thin inversion layer. In a 180 nm CMOS process a typical NMOS Vth is about 0.45 V; in a leading-edge FinFET node the regular-Vt flavours sit near 0.3 to 0.4 V.
A depletion-mode device is normally ON. A shallow implant of the same doping type as source and drain builds a channel into the silicon during fabrication, so drain current IDSS already flows at VGS = 0. You turn it off by applying a gate voltage of the opposite polarity, which depletes the channel of carriers once VGS reaches the pinch-off value (often written VP or, confusingly, still Vth). An n-channel depletion device might have Vth = -2 V.
Key fact: the polarity of Vth tells you the mode for an NMOS. Vth > 0 means enhancement, Vth < 0 means depletion. For a PMOS the signs flip: Vth < 0 is enhancement, Vth > 0 is depletion.
N-channel versus P-channel
An NMOS sits in a p-type body with n+ source and drain; conduction is by electrons and needs a positive VGS above Vth. A PMOS sits in an n-well with p+ source and drain; conduction is by holes and needs the gate to be pulled below the source by more than |Vtp|. That is why PMOS equations are written with VSG and VSD, and why the PMOS source ties to VDD while the NMOS source ties to ground in an inverter.
The practical difference is mobility. In bulk silicon electron mobility is roughly 2 to 3 times hole mobility (around 1400 versus 450 cm2/V·s for lightly doped material, lower in a real inversion layer). To get equal pull-up and pull-down current, a standard-cell designer makes the PMOS about 2 to 2.5 times wider than the NMOS. This is the origin of the familiar Wp/Wn ratio you will see in any cell library characterised with Synopsys PrimeTime or Cadence Liberate. Strained-silicon and FinFET processes narrow the gap, but the ratio rarely reaches 1.
Symbols you must be able to draw
Symbols encode the two questions directly. A broken channel line (three dashes) means enhancement: the channel is absent until induced. A solid channel line means depletion: it is already there. The arrow on the body or bulk terminal points into the channel for n-channel (p-type body to n-channel) and out of it for p-channel. Many textbooks also draw a bubble on the PMOS gate in logic diagrams. In Cadence Virtuoso the four-terminal cells you place are nmos4 and pmos4 from the analogLib, and the device model card, not the symbol, decides whether it is enhancement or depletion.
Threshold behaviour and the transfer curve
In saturation the long-channel square-law model gives ID = (k/2)(VGS - Vth)2, with k = μCox(W/L). The same equation describes both modes; only Vth moves. Plot ID against VGS and the curve of an enhancement NMOS starts at zero current to the right of the origin, while a depletion NMOS curve is shifted left so that it already carries IDSS at VGS = 0 and keeps conducting for slightly negative gate voltages. The sub-threshold region below Vth is not truly zero: current falls roughly one decade per 70 to 100 mV, which is why leakage budgets matter so much in always-on SRAM and why foundries sell high-, standard- and low-Vt (HVT, SVT, LVT) variants.
| Type | Channel at VGS = 0 | Vth sign | Turns ON when |
|---|---|---|---|
| NMOS enhancement | Absent (OFF) | Positive | VGS > Vth |
| NMOS depletion | Present (ON) | Negative | OFF only when VGS < Vth |
| PMOS enhancement | Absent (OFF) | Negative | VSG > |Vtp| |
| PMOS depletion | Present (ON) | Positive | OFF only when VGS > Vth |
Seeing the channel form
The animation below ramps the gate voltage on an enhancement NMOS. While the bar is left of the Vth mark there is no inversion layer and no electrons cross the p-substrate. The moment the bar passes Vth the channel lights up and electrons stream from source to drain.
Where each type shows up in real design
- Enhancement NMOS and PMOS: every logic gate, SRAM bit-cell and standard cell. Normally-OFF behaviour means a powered-up chip with undefined gate voltages does not short VDD to ground. Synthesis tools such as Synopsys Design Compiler or Cadence Genus simply choose among HVT/SVT/LVT versions of these cells.
- Depletion NMOS: the pull-up load in 1970s single-polarity NMOS logic (gate tied to source gives a roughly constant current), and today in start-up circuits and bias current sources that must conduct before any supply is stable. Discrete parts such as the BSS139 are used this way.
- Power P-channel enhancement: high-side load switches and reverse-battery protection, because the gate is driven relative to the supply rail without a charge pump.
- Analog IP: thick-oxide, native (zero-Vt) and low-Vt NMOS devices give extra headroom in current mirrors. A native device is effectively Vth near 0 V, sitting between the two modes. SPICE-level checks in HSPICE or Spectre confirm the sign and value of Vth, and Siemens Calibre extraction verifies the layout matches the schematic device type.
Interview trap: you cannot tell a depletion device from an enhancement device by looking at layout geometry alone. The difference is a channel implant, so it is a process option and a model-card flag.
Once you can classify a device on sight, the next step is biasing and small-signal modelling: see the MOSFET small-signal model for gm, ro and gain. Teams building these skills for tape-out work often pair theory with hands-on design flow training at ChipXpert's VLSI training programmes.
Want to practise drawing, biasing and simulating all four device types? Join the analog tracks in our CourseTron courses and work through guided SPICE labs.
Frequently Asked Questions
Why is almost all CMOS enhancement-mode?
Because a normally-OFF device draws no static current when its input is at the rail, and complementary pairs conduct only during switching. A depletion device would leak whenever its gate is at zero, wasting power and reducing noise margins.
Can a depletion MOSFET be turned off?
Yes. Apply a gate voltage beyond the pinch-off value in the opposite polarity: roughly VGS below -2 V for the NMOS example in this article, or a positive VGS for a PMOS depletion device.
Why is the PMOS usually wider than the NMOS?
Hole mobility is lower than electron mobility, so a PMOS gives less current for the same W/L. Making it about 2 to 2.5 times wider balances rise and fall times in an inverter.
Is the sign of Vth always positive for NMOS?
No. A positive Vth marks enhancement mode; a negative Vth on an n-channel device means depletion mode. For PMOS enhancement the threshold is negative.