RC Circuit Transient Response

In short: A capacitor charged through a resistor obeys the first-order ODE RC·dv/dt + v = Vs, whose solution v(t) = Vs(1 − e^(−t/RC)) rises 63.2% in one time constant, reaches 99.3% in five, and needs about 6.9 time constants to settle within 0.1%.

Why this one equation shows up everywhere

Every wire in a chip is a resistor driving a capacitor. A gate output charging the input of the next stage, a bias node being filtered, an ADC sampling switch charging its hold capacitor, a power-on reset delay: all of them reduce to the same first-order network. If you can derive its step response from scratch and quote settling numbers from memory, you can estimate delay, bandwidth and sampling accuracy on a whiteboard before any simulator opens. That is exactly why interviewers keep asking it. If you only need the definition of the time constant, start with our RC time constant primer; here we go the whole way from the differential equation to settling error budgets.

Setting up the circuit and the ODE

Take a step source Vs that jumps from 0 V to 3.3 V at t = 0, a series resistor R = 10 kΩ, and a capacitor C = 100 nF to ground, initially uncharged. The output is the capacitor voltage v(t).

Kirchhoff's voltage law around the loop gives Vs = i·R + v. The capacitor relation is i = C·dv/dt. Substituting:

RC · dv/dt + v = Vs        (first-order, linear, constant coefficients)
tau = RC = 10k x 100n = 1 ms

Solving it two ways

Separation of variables. Rearrange to dv/(Vs − v) = dt/τ. Integrate from v = 0 at t = 0: −ln(Vs − v) + ln(Vs) = t/τ, so Vs − v = Vs·e^(−t/τ), and

v(t) = Vs · (1 − e^(−t/tau))
i(t) = (Vs/R) · e^(−t/tau)

Natural plus forced response. The general solution is a particular solution (the steady state, v = Vs) plus a homogeneous solution A·e^(−t/τ). The initial condition v(0) = 0 forces A = −Vs. This second view generalises: for any initial voltage V0, the answer is v(t) = Vs + (V0 − Vs)·e^(−t/τ). Memorise that form, because it also handles discharge (Vs = 0) and a step between two non-zero levels.

Key fact: The initial slope is Vs/τ = 3.3 V/ms. Had the capacitor kept charging at that rate it would hit Vs exactly at t = τ, but the shrinking resistor voltage curbs it, so it only reaches 63.2%.

Reading the curve: voltages at each time constant

Settling time, rise time and delay

Designers rarely care about "five time constants"; they care about an error budget. Solving e^(−t/τ) = ε gives t = τ·ln(1/ε). So 1% settling takes 4.6τ, 0.1% takes 6.9τ, and an N-bit accuracy target (error ≤ 1/2^(N+1) of full scale) takes about 0.69·(N+1)·τ. A 12-bit sampling switch charging its hold capacitor therefore needs roughly 9τ, which is why SAR ADC designers size switch on-resistance against the acquisition window.

Two other metrics come from the same formula. The 10%–90% rise time is τ·ln 9 ≈ 2.2τ (2.2 ms here), and the 50% propagation delay is τ·ln 2 ≈ 0.69τ (0.69 ms). The Elmore delay used in static timing analysis is exactly this idea: tools such as Synopsys PrimeTime and Cadence Tempus model a net as an RC tree and approximate each sink delay by a sum of R·C products.

Key fact: Rise time ≈ 2.2·RC and bandwidth f(−3dB) = 1/(2π·RC), so t_rise × BW ≈ 0.35. Use it to flip between time-domain and frequency-domain specs.

Watching charge flow

Notice the energy accounting too: the source supplies Q·Vs = C·Vs², but the capacitor stores only half of it (C·Vs²/2 = 544 nJ here). The other half is dissipated in R regardless of whether R is 1 Ω or 1 MΩ. That 50% loss is the root of adiabatic-charging research and a reminder that CMOS dynamic power is C·V²·f, independent of driver strength.

Common mistakes and how to check yourself

• Forgetting the initial condition. A node pre-biased at 1 V does not start from zero; use Vs + (V0 − Vs)e^(−t/τ).
• Ignoring source or load resistance. A 50 Ω source in series adds to R, and a resistive load forms a divider, so the final value is Vs·RL/(R+RL) with a faster τ = (R‖RL)·C.
• Trusting five-τ rules for high-resolution systems. 16-bit accuracy needs about 11τ.
• Not validating in simulation. Run a transient in Cadence Spectre, Synopsys HSPICE or Siemens Eldo with a PWL step and read the 63.2% crossing; it should land at 1 ms within the tolerance of the timestep. If it does not, tighten the maximum step or check for parasitic capacitance you forgot.

The same machinery extends to second-order RLC circuits, where the damping ratio decides between ringing and monotonic settling; see our RLC step response guide. For hands-on practice with real flows, the CourseTron analog courses pair derivations like this with simulator labs, and teams that need silicon-grade analog help can look at Avecas design services.

Ready to go from derivations to working analog blocks? Explore the CourseTron analog design courses and practise transient analysis on real circuits.

FAQ

Why does the capacitor never reach exactly Vs?

The charging current is proportional to the remaining voltage difference, so each instant closes a fixed fraction of the gap. The exponential approaches Vs asymptotically; in practice it is within noise or quantisation after about 7τ to 10τ.

Is 5τ the same as "fully charged"?

Only to about 0.7%. That suits many digital and filter uses, but precision ADC acquisition or reference settling needs 7τ to 11τ depending on the resolution.

How does the step response relate to cut-off frequency?

The same τ sets both: f(−3dB) = 1/(2πRC) and 10–90% rise time = 2.2RC, so rise time times bandwidth is about 0.35.

Does the step amplitude change the time constant?

No. For a linear RC the time constant depends only on R and C. Doubling Vs doubles every voltage but the 63.2% crossing still happens at t = τ.

Related training and mentoring is also available from ChipXpert VLSI training.