In short: A capacitor charged through a resistor follows V(t) = Vs(1 − e^(−t/RC)), so after one time constant τ = RC it reaches 63.2% of its final value, and discharging leaves 36.8% after τ.
Why the RC circuit is worth deriving
Almost every analog block you will ever debug contains an RC pair, either drawn on purpose or inflicted by the layout. A reset pin with a pull-up and a capacitor, a sample-and-hold switch driving its hold capacitor, a long metal route in Innovus or Virtuoso with extracted parasitics: all of them are first-order systems. If you can derive the response of one resistor and one capacitor, you can reason about settling time, bandwidth and delay without opening a simulator. Interviewers know this, which is why "why is it 63%?" shows up so often.
Setting up the differential equation
Take a step source Vs, a series resistor R and a capacitor C that starts at 0 V. Kirchhoff's voltage law around the loop gives Vs = i·R + vC. The capacitor obeys i = C·dvC/dt. Substitute the current and you get one equation in one unknown:
RC · dv/dt + v = Vs (v(0) = 0)Rearrange to separate variables: dv/(Vs − v) = dt/(RC). Integrate both sides from 0 to t, and the left side gives −ln(Vs − v) evaluated between the limits:
−ln[(Vs − v)/Vs] = t/RC
v(t) = Vs · (1 − e^(−t/RC))
i(t) = (Vs/R) · e^(−t/RC)Notice the current is the mirror image of the voltage: the capacitor draws maximum current at t = 0 when it looks like a short circuit, and the current decays to zero as the capacitor approaches an open circuit. The resistor voltage, vR = Vs·e^(−t/RC), falls as the capacitor voltage rises, and the two always add up to Vs.
What τ = RC really means
Set t = τ = RC in the charging equation and the exponent becomes −1. Since e−1 ≈ 0.368, the capacitor sits at 1 − 0.368 = 63.2% of Vs. Nothing magical, it is simply what an exponential does after one unit of its own time scale. During discharge, v(t) = V0·e^(−t/RC), so the same instant leaves 36.8% of the starting voltage.
Key fact: the tangent to the charging curve at t = 0 has slope Vs/τ. If the capacitor kept charging at its initial rate, it would reach Vs exactly at t = τ; the real curve bends over and has only reached 63.2% by then.
Units check: ohms times farads is seconds. A 10 kΩ resistor with a 100 nF capacitor gives τ = 10,000 × 100×10−9 = 1 ms. Double either component and τ doubles.
The numbers worth memorising
| Elapsed time | Charging (% of Vs) | Discharging (% of V0) |
|---|---|---|
| 0.693 τ | 50.0% | 50.0% |
| 1 τ | 63.2% | 36.8% |
| 2 τ | 86.5% | 13.5% |
| 3 τ | 95.0% | 5.0% |
| 5 τ | 99.3% | 0.7% |
The 50% point at 0.693τ (that is ln 2) is the propagation-delay figure used in static timing: the Elmore delay of an RC net is basically τ, and the 50% crossing sits at about 0.69 of it. The 10% to 90% rise time is ln(9)·τ ≈ 2.2τ, which is exactly how an RC low-pass filter converts to bandwidth, a relationship explored in our RC low-pass filter response article: f−3dB = 1/(2πRC), so tr ≈ 0.35/f−3dB.
Seeing it move: charge flowing into the capacitor
The animation below shows charge carriers marching through the resistor into the capacitor. Watch the spacing: carriers are dense and fast at the start, then thin out as the capacitor voltage opposes the source and the current dies away.
Practical design examples
- Power-on reset: a 100 kΩ pull-up with 1 µF gives τ = 100 ms. If the reset input threshold is 70% of VDD, the delay is τ·ln(1/0.3) ≈ 1.2τ = 120 ms.
- Sample-and-hold: a 12-bit ADC needs the hold capacitor within half an LSB, an error of 2−13. Settling needs ln(8192) ≈ 9τ, so with a 1 kΩ switch and 5 pF, τ = 5 ns and the acquisition window must exceed about 45 ns.
- Interconnect: in a PnR flow, extracted resistance and capacitance per net feed the delay calculator. Tools such as Synopsys PrimeTime and Cadence Tempus report net delay from the distributed RC tree, and its leading term is the same RC product you just derived.
Key fact: "settled" depends on your accuracy target. 1% needs 4.6τ, 0.1% needs 6.9τ, and an n-bit converter needs roughly (n+1)·0.693τ.
Common mistakes in interviews
- Saying the capacitor is "fully charged after τ". It is 63.2% charged; practical settling takes 4 to 5τ.
- Forgetting initial conditions. If the capacitor starts at V0 and the source goes to Vs, use v(t) = Vs + (V0 − Vs)·e^(−t/τ). Charging and discharging are the same formula.
- Ignoring source resistance. A 50 Ω function generator in series with R adds to the effective resistance, and a scope probe's 10 pF adds to C.
- Treating a transistor driver as an ideal resistor. A MOS switch's on-resistance changes with signal level, so τ is not constant during a transition.
The same machinery extends to filters and compensation networks. If you want to see how τ turns into magnitude and phase, continue with the low-pass filter article or the related op-amp slew rate and settling time piece. Teams that want hands-on training on parasitic extraction can look at ChipXpert's VLSI training programmes.
Ready to go beyond one resistor and one capacitor? Explore the analog design track on CourseTron courses and practise these derivations with guided simulations.
Frequently asked questions
Why is the charging point exactly 63.2%?
Because 1 − e−1 = 0.632. After one time constant the exponent is −1, and e−1 = 0.368 is the fraction still remaining to be charged.
How many time constants until a capacitor is fully charged?
Mathematically never, but 5τ reaches 99.3% and is the usual engineering rule; high-resolution converters need 7 to 10τ.
Does the charging time depend on the supply voltage?
No. τ = RC depends only on R and C. A larger Vs raises the final voltage and the current, but the percentage curve against time is identical.
How does τ relate to the cutoff frequency?
f−3dB = 1/(2πτ). A 1 ms time constant corresponds to roughly 159 Hz.