In short: Slew rate is the large-signal speed limit set by how fast an amplifier's internal node can be charged, while settling time is the total small-plus-large-signal interval needed to land within an error band — together they, not bandwidth alone, cap how quickly a real amplifier or DAC can deliver an accurate output.
Engineers new to analog design often treat gain-bandwidth product as the only speed number that matters. In practice, when a step arrives at the input, two very different physical regimes govern the response, and the datasheet number that wins depends entirely on the amplitude. Understanding the handoff between slew rate and settling time is what separates a DAC that hits 16-bit accuracy in a microsecond from one that looks fast on a Bode plot but smears every code transition.
Small signal vs large signal: two different worlds
A step response has two personalities. For a small step — say a few millivolts at the output — every transistor in the signal path stays in its linear, small-signal operating region. The circuit behaves like a linear time-invariant system, so the response is governed by poles, zeros and the closed-loop bandwidth. This is the linear settling regime, and it produces the familiar exponential or ringing approach to the final value.
For a large step, the input stage saturates. A differential pair can only steer its tail current Itail to one side; once fully steered, the output cannot move faster than that fixed current can charge the compensation or load capacitance. The output ramps as a straight line, not an exponential. That linear ramp is slewing, and its slope is the slew rate:
SR = Itail / Cc
Rule of thumb: If the required output change divided by the available settling time exceeds the slew rate, the amplifier is slew-limited and no amount of extra bandwidth helps — you must raise the bias current or lower the capacitance.
What "settling time" actually measures
Settling time ts is the interval from the input step to the moment the output enters — and stays inside — a defined error band around its final value. The band is the critical qualifier: 1% settling and 0.001% settling can differ by an order of magnitude on the same amplifier. For data converters the band is expressed in LSBs. A 16-bit DAC settling to ½ LSB must land inside roughly 0.00076% of full scale, so a tiny amount of residual ringing or slow-tail recovery that a 1% spec would ignore becomes the dominant delay.
Settling decomposes into three parts: the slew interval (large signal), the linear settling ring-down (small signal), and often a sneaky long tail caused by thermal effects, dielectric absorption in the feedback capacitor, or incomplete charge recovery in the input pair. That thermal tail is why a part can reach 0.1% in 100 ns but need another 2 µs to crawl the last few bits.
| Target accuracy | Error band | Time constants needed |
|---|---|---|
| 1% | 10-2 | ~4.6 τ |
| 0.1% (≈10-bit) | 10-3 | ~6.9 τ |
| 0.0015% (16-bit) | ½ LSB | ~11 τ |
Why bandwidth isn't enough: A single-pole system needs n·ln(2) ≈ 0.69n time constants to settle to n bits. Doubling resolution adds time constants linearly, so settling time grows even when gain-bandwidth stays fixed.
Slewing in motion
A worked number
Take an op-amp with SR = 20 V/µs driving a 10 V full-scale step. The pure slew phase alone takes 10 V ÷ 20 V/µs = 0.5 µs just to traverse the swing. If the small-signal bandwidth corresponds to τ = 50 ns and you need 16-bit accuracy (≈11 τ), linear settling adds another 550 ns. Total settling ≈ 1.05 µs — more than double what the bandwidth figure alone would suggest, because the slew phase is "wasted" time where feedback is open. This is exactly why high-speed DAC output buffers are specified with a dedicated settling-time plot rather than a bandwidth number.
Design levers and how we verify them
- Raise SR: increase tail current or use a class-AB / slew-boost input stage so the ramp phase shrinks.
- Shrink the error tail: choose feedback capacitors with low dielectric absorption (C0G/NP0, not X7R) and manage self-heating.
- Balance phase margin: under-compensation speeds linear settling but adds ringing that re-enters the band repeatedly, lengthening ts.
- Trade bandwidth for current: SR and quiescent current are coupled, so slewing is ultimately a power budget.
In a modern flow, you confirm all of this in transient simulation. Cadence Spectre or Synopsys HSPICE run the large-signal step, a .measure statement extracts the exact band-entry time, and a Monte Carlo sweep checks that process and temperature corners still settle. Siemens (Analog FastSPICE) is common for verifying settling across a full converter's digital codes. The same discipline applies whether you are closing a discrete board or a SAR DAC macro.
For the broader signal-integrity view — how these same ramp and settling limits show up on high-speed digital links — our design-services team at Avecas analog and mixed-signal design services works these trade-offs on real tapeouts, and the intuition carries straight back to the amplifier bench.
Want to measure settling time on real silicon and tune slew-limited buffers hands-on? Join the Analog & Mixed-Signal track on our CourseTron courses and work through live SPICE labs.
To go deeper on the mechanism behind the ramp slope, read our companion piece on slew rate fundamentals, and to see how feedback stability shapes the small-signal tail, see phase margin and stability.
Frequently asked questions
Is settling time just 1/bandwidth?
No. Bandwidth sets the small-signal time constant, but settling also includes the slew phase and any thermal tail. A fast amplifier that slews slowly can have a long settling time despite a wide bandwidth.
Why does the error band change settling time so much?
Settling is exponential in the linear phase, so each additional decade of accuracy costs roughly 2.3 more time constants. Going from 1% to 0.001% can more than double the total time.
How is slew rate different from rise time?
Rise time is a small-signal, bandwidth-limited measure; slew rate is the large-signal maximum slope set by current over capacitance. They only coincide for amplitudes small enough that the input pair never saturates.
Does slewing distort signals?
Yes — if a sine wave's maximum dV/dt (2π·f·Vpeak) exceeds the slew rate, the output turns into a triangle wave. This sets the full-power bandwidth, always lower than the small-signal bandwidth.