In short: Slew rate is the maximum rate at which an op-amp's output voltage can change (volts per microsecond), set by a fixed internal charging current into the compensation capacitor — it caps large-signal bandwidth and is a hard nonlinear limit entirely separate from the small-signal −3 dB frequency.
Ask a junior analog engineer why their sine wave turned into a triangle at high frequency and they will often reach for "bandwidth." They are usually wrong. The culprit is almost always slew rate — a large-signal limitation that behaves nothing like the gentle roll-off you see on a Bode plot. Understanding the difference is one of the fastest ways to separate someone who has only read datasheets from someone who has actually debugged a signal chain.
What slew rate actually is
Slew rate (SR) is defined as the maximum rate of change of the output voltage:
SR = max |dVout/dt|, expressed in V/µs.
A general-purpose part like the venerable TL072 slews at about 13 V/µs. A precision part such as the OP07 manages only around 0.3 V/µs. A fast part like the LT1363 reaches 1000 V/µs. These numbers are not arbitrary — they fall directly out of the internal topology.
In a classic two-stage Miller-compensated op-amp, the input differential pair steers a fixed tail current into the gain stage, whose dominant pole is set by the Miller compensation capacitor Cc. When the input sees a large step, the differential pair fully switches: one side takes the entire tail current Itail, and that current is the only thing available to charge Cc. Since i = C·dV/dt, the output cannot change faster than:
SR = Itail / Cc
Slew rate is a current-starvation effect, not a frequency effect. During slewing the op-amp is operating open-loop and nonlinearly — the input stage is saturated, feedback is momentarily broken, and the virtual short at the inputs does not hold.
How slew rate limits large-signal bandwidth
This is the result every interviewer wants to hear. For a sine wave Vout = Vp·sin(2πft), the steepest slope occurs at the zero crossing and equals 2π·f·Vp. The op-amp can reproduce the sine undistorted only while this peak slope stays below the slew rate. Setting them equal gives the full-power bandwidth (FPBW):
fmax = SR / (2π·Vp)
Plug in numbers: a TL072 at 13 V/µs driving a ±10 V (Vp = 10) output can only stay clean up to roughly 13×106 / (2π·10) ≈ 207 kHz. Yet its small-signal gain-bandwidth product is 3 MHz. The two numbers differ by more than 10×, and the gap grows as amplitude grows.
Slew rate vs. small-signal frequency response
This is the distinction that trips people up. The two limits come from completely different physics:
| Property | Small-signal bandwidth | Slew rate |
|---|---|---|
| Nature | Linear, frequency-domain | Nonlinear, time-domain |
| Set by | GBW / closed-loop gain, pole locations | Itail / Cc |
| Depends on amplitude? | No | Yes (worse for large Vp) |
| Feedback intact? | Yes | No — input stage saturated |
| Measured with | Small sine, Bode plot | Large step response |
Practically: if you shrink the output amplitude enough, slewing disappears and you are left with only the small-signal −3 dB roll-off. That is exactly how you tell them apart on the bench. Drive the amplifier with a small (say 100 mV) sine and sweep frequency — the −3 dB point you find is the true small-signal bandwidth. Now increase amplitude to full scale: the clean frequency drops dramatically, and a scope shows triangular edges. That amplitude-dependent collapse is the fingerprint of slew limiting.
A rule of thumb for step response: the full-swing output needs t ≈ ΔV / SR just to ramp, before the normal exponential settling even begins. A 10 V step on a 10 V/µs part costs 1 µs of pure slewing on top of settling time.
Where it bites in real designs
- Audio & DACs: reconstruction filters and I/V stages must slew fast enough for full-scale high-frequency content, or you get slew-induced distortion (SID) that no amount of feedback removes.
- Pipelined ADC drivers: the driver must settle a full-scale step within a sampling period; insufficient SR shows up as code-dependent settling errors.
- Power/gate drivers: here you often want controlled slew to limit EMI and ringing.
In practice you verify this in simulation before committing silicon. A transient step in Cadence Spectre or Synopsys HSPICE will immediately reveal the ramp-limited edge, and a .meas statement on dV/dt extracts SR directly; Siemens Eldo and the AFS simulator give the same picture. On the verification side, these large-signal transients are part of the standard analog characterization sweep. If you are building this intuition for interviews or tapeout work, our hands-on analog track walks through exactly these measurements.
Boosting slew rate
From SR = Itail/Cc the levers are obvious: raise the tail current, shrink Cc (at the cost of phase margin), or use clever input stages. Class-AB and slew-enhanced ("current-on-demand") input stages break the fixed-tail assumption by delivering extra charging current only during large transients, giving fast slewing without burning static power. Feedforward and folded-cascode topologies tune the same trade-off. For custom amplifier IP where these trade-offs must be optimized at the transistor level, teams often lean on a dedicated design house such as Avecas analog design services rather than reinventing the input stage.
For the companion linear picture — poles, zeros, gain-bandwidth product and phase margin — read our deep dive on op-amp frequency response, and for the time-domain cousin see op-amp settling time. Both build directly on the ideas here.
Want to measure slew rate, GBW and settling on real parts and in SPICE? Join the CourseTron Analog IC Design track and run the full large-signal characterization lab. Browse courses →
Frequently asked questions
Is slew rate the same as bandwidth?
No. Bandwidth (GBW / −3 dB) is a linear, small-signal, amplitude-independent limit. Slew rate is a nonlinear, large-signal limit set by charging current and gets worse as output amplitude increases. A part can have huge bandwidth yet modest slew rate.
Why does my sine wave look like a triangle?
Because the required slope 2πfVp has exceeded the slew rate. The output can only ramp at its maximum dV/dt, producing straight edges instead of curves. Reduce amplitude or frequency, or pick a faster op-amp.
How do I calculate the maximum undistorted frequency?
Use the full-power bandwidth formula fmax = SR / (2π·Vp), where Vp is the peak output amplitude. For a 10 V/µs amp at ±5 V peak, fmax ≈ 318 kHz.
Does negative feedback fix slew limiting?
No. During slewing the input stage is saturated and the loop is effectively broken, so feedback cannot correct it. This is why slew-induced distortion is so insidious — more loop gain does not help.