Phase margin and stability in analog feedback

In short: Phase margin is how much extra phase lag a feedback loop can tolerate at its unity-gain frequency before it oscillates. You read it off a Bode plot as 180° minus the loop phase where the gain crosses 0 dB, and you tune it with compensation. For most analog circuits, aim for roughly 45°–60° of phase margin for a clean, non-ringing response.

What is phase margin?

Phase margin is a stability metric for any negative-feedback system. A feedback loop subtracts a scaled copy of its output from its input. That subtraction is only truly “negative” if the signal arrives back in the right phase. Every real amplifier adds delay, and delay shows up as phase lag that grows with frequency. If the loop ever reaches a point where the signal is delayed by a full 180° and the loop still has a gain of one or more, the feedback has quietly turned positive and the circuit oscillates.

Phase margin measures how far you are from that cliff. You find the frequency where the loop gain magnitude equals 1 (0 dB) — the gain crossover frequency — and ask how much phase lag is left before you hit the dangerous 180°. Formally:

• Phase margin = 180° + ∡(loop gain) at the 0 dB crossover (the loop phase is negative, so this is really 180° minus the amount of lag).
• A large phase margin means the loop is comfortably stable and damped.
• A phase margin near 0° means the circuit is on the edge of sustained oscillation.

Reading phase margin from a Bode plot

The Bode plot is the natural home for phase margin because it draws loop gain and loop phase against frequency on the same log axis. The recipe is mechanical:

1. Plot the open-loop gain magnitude in dB versus frequency.
2. Find where that curve crosses 0 dB — the gain crossover frequency, f_c.
3. Drop down to the phase curve at that same f_c and read the phase.
4. Phase margin is the gap between that phase and −180°.

A companion number, gain margin, works the other way: find the frequency where the phase hits −180°, then read how many dB below 0 dB the gain sits there. Both margins must be positive for a stable loop, but in analog design phase margin is usually the binding constraint.

Why poles erode phase margin

Every pole in the loop (an RC node, the output load, the dominant internal node of an op-amp) contributes up to 90° of phase lag and bends the gain down by 20 dB/decade. One pole alone can only reach 90° of lag, so a single-pole loop is unconditionally stable. Trouble starts when a second pole falls near or below the crossover: now the loop can accumulate close to 180° of lag right where the gain is still above one. The closer the two poles sit, the steeper the gain slope at crossover (approaching 40 dB/decade) and the smaller the phase margin.

A useful rule of thumb: if the loop crosses 0 dB on a clean −20 dB/decade slope, you are in good shape; if it crosses on a −40 dB/decade slope, phase margin is probably marginal or negative.

Compensation: buying back phase margin

Compensation reshapes the loop so the gain is safely below one before the phase runs out. The common techniques:

Dominant-pole (Miller) compensation

Deliberately add a large capacitor to push the first pole to a very low frequency. This drags the whole gain curve down so it crosses 0 dB while only the dominant pole is active — before the second pole adds its lag. In op-amps the Miller capacitor across the second stage does this and also splits the two poles apart (pole splitting), widening the gap and lifting phase margin.

Lead compensation (a zero)

A zero adds positive phase, locally cancelling some lag near the crossover. Placing a zero just below f_c can restore 20–30° of phase margin without heavily slowing the loop — the basis of the series RC “Miller with nulling resistor” fix that also tames the troublesome right-half-plane zero of a two-stage amplifier.

Reducing loop gain

Lowering DC loop gain shifts the crossover to a lower frequency, where less phase has accumulated. It is the cheapest fix but costs you accuracy and bandwidth.

Phase margin and the time-domain response

Margins are a frequency-domain idea, but their payoff is visible in the step response. For a dominant two-pole loop the mapping is tight:

• ~65°: near-critically damped, <5% overshoot — the usual target.
• 45°: noticeable overshoot (~23%) and ringing that settles after a few cycles.
• <30°: heavy ringing, long settling, sensitive to load.
• 0°: sustained oscillation — the circuit is an oscillator, not an amplifier.

This is why datasheets quote phase margin and why you always check it across process, temperature, and — critically — load capacitance, which adds an output pole that can silently eat your margin.

phase margin — FAQ

What is a good phase margin value?

Between 45° and 60° for general-purpose feedback, with ~65° giving the best speed-versus-overshoot trade-off. Values above 70° are very safe but slow; below 45° the response rings.

What is the difference between phase margin and gain margin?

Phase margin is the spare phase at the 0 dB gain crossover; gain margin is the spare gain (in dB) at the −180° phase crossover. Both should be positive, but phase margin usually governs analog stability.

Why does capacitive load reduce phase margin?

A load capacitor forms a new pole with the amplifier's output resistance. That pole adds phase lag near the crossover, shrinking phase margin and often causing ringing — which is why many op-amps specify a maximum capacitive load or need an isolation resistor.

How do I measure phase margin in simulation?

Break the loop, inject a small-signal AC source, run an AC sweep of loop gain, then read 180° plus the loop phase at the frequency where the magnitude passes 0 dB. SPICE stability (STB) analysis automates this.

Related: op-amp design basics · Glossary · all courses.