Analog

Operational amplifier design basics

By CourseTron Team ·  7 min read ·  Updated Oct 2026 💬 𝕏 in f
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    In short: Op-amp design is the craft of shaping a high-gain differential amplifier so it is accurate, fast enough, and stable when wrapped in feedback. The classic learning vehicle is the two-stage CMOS topology: a differential pair for gain, a common-source stage for swing, and a Miller capacitor for compensation. Get the gain, bandwidth and phase-margin trade-off right and almost everything else follows.

    What Is op-amp design?

    Op-amp design is the process of choosing a circuit topology, transistor sizes and bias currents so that an operational amplifier meets a target set of specifications — DC gain, gain-bandwidth product, slew rate, input offset, noise and stability — while the device sits inside a negative-feedback loop. An op-amp is almost never used open-loop; it is used as a near-ideal gain block that forces its two inputs to the same voltage. Your job as a designer is to make that "near-ideal" assumption hold over the frequency range, supply voltage and load your application cares about.

    Three numbers dominate the conversation: how much gain the amplifier delivers, how much bandwidth it keeps, and how much phase margin remains when you close the loop. These three fight each other, and resolving that fight is the real content of op-amp design.

    Key fact: For a single-pole amplifier the gain-bandwidth product is constant. An op-amp with 100 dB (10⁵) DC gain and a 1 MHz gain-bandwidth product has its first (dominant) pole at just 10 Hz — the gain is already rolling off far below where most people expect.

    Gain and bandwidth: the core trade-off

    Open-loop DC gain (A₀) sets how accurately feedback can enforce the virtual-short condition. The closed-loop gain error is roughly 1/(A₀β), where β is the feedback factor, so more open-loop gain means a more precise amplifier. In CMOS a single stage gives gain of order gₘrₒ — transconductance times output resistance — which is often only 30–40 dB. That is why we cascade two stages: multiplying two gₘrₒ products can reach 70–100 dB.

    Bandwidth is the other half. The gain-bandwidth product (GBW) equals gₘ₁/(2πC₰), where gₘ₁ is the input-stage transconductance and C₰ is the compensation capacitor. Notice what this means: you buy speed with input transconductance (more bias current, wider devices) and you pay it back with the capacitor you add for stability. Designers spend much of their time trading these two off against power and area.

    • Want more gain? Lengthen devices or add cascodes — but output swing and bandwidth suffer.
    • Want more bandwidth? Raise gₘ₁ or shrink C₰ — but phase margin and slew rate are affected.
    • Want more slew rate? Raise the tail current relative to C₰ (SR ≈ Iₜₐⁱₓ/C₰).
    Single-Pole Open-Loop Gain: 100 dB, 10 Hz, 1 MHz 100 dB 0 dB 1101001k10k100k1M10M A₀ = 100 dB (10⁵) Dominant pole: 10 Hz −20 dB/decade GBW = 1 MHz frequency (Hz, log scale) CourseTron · coursetron.com
    Open-loop response of the key-fact example: 100 dB DC gain, 10 Hz dominant pole, 1 MHz gain-bandwidth product.

    The two-stage topology, block by block

    The textbook workhorse is the two-stage Miller-compensated op-amp. The first stage is a differential pair with a current-mirror load that converts the differential input into a single-ended current and provides most of the gain. The second stage is a common-source amplifier that adds more gain and, crucially, the large output voltage swing. A Miller capacitor bridges the second stage to split the two poles apart.

    Two-Stage CMOS Op-Amp V+ V− Diff Pair gain, gm1 Common-Source gain, swing Vout Cc Stage 1 sets gain and speed → Stage 2 sets swing → Cc sets stability CourseTron · coursetron.com
    Signal path through a two-stage Miller-compensated op-amp.

    Why two stages and not one

    A single stage must deliver both the gain and the output swing at the same node, and those requirements pull in opposite directions — high gain wants a high-impedance node, large swing wants headroom. Splitting the amplifier lets the first stage optimise for gain and noise while the second optimises for swing and drive. The cost is a second pole, which is exactly the problem compensation solves.

    Compensation: making it stable

    With two gain stages you have two low-frequency poles. If both sit near the unity-gain frequency, the loop accumulates close to 180° of phase shift and the amplifier rings or oscillates when you close the loop. Compensation reshapes the frequency response so that only one pole dominates up to the unity-gain crossover.

    Miller compensation is the standard method. Placing a capacitor C₰ across the second stage does two things at once through the Miller effect: it pushes the first-stage pole down to a very low frequency (pole splitting) and pushes the second-stage pole up and out of the way. The result is a clean single-pole roll-off over most of the useful band. The animation below shows how the dominant pole moves lower as C₰ grows, trading bandwidth for phase margin.

    Pole Splitting with Cc (gain vs. frequency) |A| log f 0 dB DC gain A₀ dominant pole and unity-gain frequency move left as Cc rises Larger Cc = lower bandwidth, higher phase margin (schematic) CourseTron · coursetron.com
    As C₰ increases, the dominant pole slides toward lower frequencies and phase margin improves.

    The right-half-plane zero

    Miller compensation has a subtle side effect: current can flow forward through C₰, creating a right-half-plane (RHP) zero that adds gain but subtracts phase — the worst of both worlds for stability. The usual fix is a nulling resistor in series with C₰; sized to roughly 1/gₘ₂, it cancels the zero, and made slightly larger it can be pushed into the left half-plane to add phase margin. A current-buffer (cascode) compensation scheme achieves the same goal without the forward path.

    A practical design sequence

    Most engineers follow a repeatable recipe rather than solving everything at once:

    1. From the required phase margin (typically 60°), set C₰ relative to the load capacitance — a common rule is C₰ > 0.22 Cₒ.
    2. From the target GBW and C₰, solve for the input-stage transconductance gₘ₁, which fixes the diff-pair current and sizes.
    3. From the slew-rate spec, set the tail current (SR ≈ I/C₰).
    4. Size the second stage so its pole sits well beyond GBW, then add the nulling resistor to tame the RHP zero.
    5. Check offset, noise and output swing, then iterate in simulation across process, voltage and temperature corners.

    The spreadsheet gets you a starting point; the simulator and the corners decide whether you ship.

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    op-amp design — FAQ

    Why is 60 degrees of phase margin the usual target?

    Around 60° gives a closed-loop step response with only mild overshoot and no ringing, while keeping the amplifier reasonably fast. Less margin speeds settling at first but causes overshoot and sensitivity to process variation; much more margin is stable but sluggish.

    What limits an op-amp's gain-bandwidth product?

    GBW = gₘ₁/(2πC₰). You raise it by increasing input-stage transconductance (more current or wider devices) or by shrinking the compensation capacitor — but shrinking C₰ erodes phase margin, so GBW is ultimately capped by the stability and power budget.

    When would I choose a folded-cascode instead of a two-stage op-amp?

    A folded-cascode is a single high-gain stage that is self-compensated by its load capacitance and offers better power-supply rejection and speed, at the cost of reduced output swing. Pick it for high-speed or switched-capacitor loads; pick the two-stage when you need large rail-to-rail-ish output swing.

    What is the right-half-plane zero and why does it matter?

    The Miller capacitor lets signal feed forward from input to output, creating a zero that boosts gain while adding negative phase near the crossover — degrading stability. A series nulling resistor cancels or relocates it, which is why nearly every Miller-compensated op-amp includes one.

    Related: Phase margin and stability · Glossary · all courses.

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