MOSFET Working Principle

In short: A MOSFET is a voltage-controlled switch-and-current-source: once the gate voltage exceeds the threshold voltage (Vt) it inverts the silicon under the oxide into a conducting channel, and the drain voltage then decides whether that channel behaves like a resistor (triode) or a current source (saturation).

The structure: why a gate can control current

Take an n-channel MOSFET on a p-type substrate. Two heavily doped n+ islands, the source and the drain, sit a distance L apart. Between them, a thin insulator (SiO2 or, in modern nodes, a hafnium-based high-k stack) separates the silicon from the polysilicon or metal gate. Because the gate is insulated, it draws essentially zero DC current. It controls the device purely through an electric field, the same way a capacitor plate attracts charge.

With the gate at 0 V, the source and drain are two back-to-back p-n junctions. Whatever you apply across drain and source, one junction is reverse biased, so only leakage flows. That is the cutoff state. Everything interesting happens when the gate pulls the surface of the p-type silicon through three conditions.

Channel formation: accumulation, depletion, inversion

• Accumulation (VG < flat-band): a negative gate pulls holes to the surface. No channel, no conduction.
• Depletion (small positive VG): the gate pushes holes away, leaving immobile negative acceptor ions. The surface band bends downward but electrons are still scarce.
• Inversion (VG beyond Vt): band bending reaches about 2φF above the Fermi level, so the surface electron concentration equals the bulk hole concentration. The p-type surface has "inverted" into n-type, forming a continuous electron layer typically only 1 to 3 nm thick.

Key fact: Threshold is conventionally defined as the gate voltage at which the surface potential equals 2φF, where φF = (kT/q)·ln(NA/ni). For NA = 10¹⁷ cm^-3 at 300 K, 2φF is roughly 0.83 V.

Threshold voltage: what sets it

The gate must supply three things: cancel the work-function and fixed-charge mismatch (flat-band voltage VFB), bend the surface by 2φF, and support the depletion charge Qdep across the oxide capacitance:

Vt = VFB + 2phiF + sqrt(2*q*eps_Si*NA*2phiF) / Cox
Cox = eps_ox / tox   (tox = 4 nm  ->  Cox ~ 8.6 fF/um^2)

Higher substrate doping or thicker oxide raises Vt; thinner oxide lowers it. Foundries then tune it with threshold-adjust implants, which is why one process offers HVT, SVT, LVT and ULVT cells. An LVT device switches faster but leaks perhaps 10 to 100 times more in subthreshold, and this exact trade-off is what Synopsys Design Compiler or Cadence Genus exploit during multi-Vt leakage recovery.

Body effect. If the source sits above the bulk by VSB, the depletion region widens and Vt rises: Vt = Vt0 + γ(√(2φF+VSB) − √2φF). With γ about 0.4 V^1/2, a source at 0.5 V can push a 0.45 V device past 0.6 V. This is why stacked NMOS devices in a NAND gate and source followers lose headroom, a favourite interview follow-up.

The three regions of operation

Define the overdrive Vov = VGS − Vt. The drain voltage then puts the device in one of three modes.

Here k = μnCox(W/L). Worked example: in a 180 nm process, μnCox is about 300 µA/V². For W/L = 10, k = 3 mA/V². With Vt = 0.45 V and VGS = 0.95 V, Vov = 0.5 V, so saturation current is 0.5 × 3 mA/V² × 0.25 V² = 0.375 mA. For small VDS = 0.1 V in triode, the channel looks like a resistor of 1/(k·Vov) = 667 Ω.

Why saturation flattens: pinch-off

The channel is not uniform. The gate-to-channel voltage at distance x from the source is VGS − V(x), so the inversion charge falls toward the drain. When VDS reaches Vov, the gate-to-channel voltage at the drain end drops to Vt and the inversion charge there vanishes: the channel is pinched off. Carriers do not stop; they are swept across the thin pinched region by the strong lateral field. Beyond that, extra VDS drops across this short depleted gap and barely changes the current, hence a current source.

The residual slope comes from channel-length modulation: the pinch-off point creeps toward the source, shrinking effective L. That slope sets output resistance ro ≈ 1/(λID). With λ = 0.1 V^-1 and ID = 0.375 mA, ro is about 27 kΩ, which caps the intrinsic gain gm·ro of an analog stage.

Where the textbook model breaks

• Velocity saturation: below roughly 250 nm, carriers hit a speed limit near 10⁷ cm/s, so ID grows almost linearly with Vov instead of quadratically.
• Subthreshold conduction: below Vt, ID falls exponentially, about one decade per 80 to 100 mV. This is the root of standby leakage.
• DIBL and short-channel Vt roll-off: a large VDS lowers the source barrier and reduces Vt, which is partly why FinFETs and gate-all-around devices wrap the gate for better electrostatic control.

Key fact: Production SPICE models (BSIM-CMG, BSIM4) use none of the square-law formulas directly. They are surface-potential or charge-based fits, so use hand equations for intuition and Spectre, HSPICE or Siemens Eldo for numbers.

In practice, designers bias analog devices at Vov of 150 to 250 mV for gain per current, and treat digital transistors as switches that spend most of their time in cutoff or deep triode. The full I-V families and extraction techniques continue in MOSFET characteristics, and once you can bias a device you can move on to the small-signal model (gm, ro, and the hybrid-pi equivalent). If you want the same fundamentals applied in layout, verification and sign-off, ChipXpert VLSI training covers it with live tool labs.

Ready to go from theory to simulation? Explore the analog design track in our CourseTron courses and bias real MOSFETs yourself.

FAQ

Is the threshold voltage the point where the MOSFET suddenly turns on?

No. Current rises exponentially below Vt (weak inversion) and smoothly through it. Vt is a defined reference, such as the gate voltage at which surface potential equals 2φF or at which ID reaches a fixed small value like 100 nA × W/L.

What is the difference between triode and saturation?

In triode, VDS < VGS − Vt, the channel extends to the drain and current depends on both VGS and VDS. In saturation, VDS ≥ VGS − Vt, the channel is pinched off at the drain and current depends almost only on VGS.

Why does a PMOS use the same equations with reversed signs?

The PMOS conducts with holes, so VGS, VDS and Vt are all negative. The physics is identical, but hole mobility is roughly 2 to 3 times lower, which is why PMOS widths are larger in CMOS gates.

Is "saturation" in a MOSFET the same as in a BJT?

No, the names are confusingly opposite. MOSFET saturation is the constant-current, amplifying region, while BJT saturation is the heavily-on switch region.