In short: Fixed bias lets the collector current scale one-for-one with beta, collector-feedback bias halves that sensitivity through negative feedback, and a voltage-divider with an emitter resistor makes the Q-point almost independent of beta, which is why it is the default in discrete designs.
Why bias at all, and why beta is the enemy
A BJT amplifier only behaves linearly when the transistor sits at a stable DC operating point, the Q-point, with the collector at roughly mid-supply so the output can swing both ways. The trouble is that the current gain beta (hFE) is the least controlled parameter on a datasheet. A small-signal part such as the 2N3904 lists hFE from about 100 to 300 at 10 mA, and it moves with temperature by roughly 0.5 to 1 percent per degree Celsius. A bias network that depends on beta therefore hands you a different amplifier on every unit and every hot day.
The standard interview question is simple: "Given beta between 100 and 200, which bias scheme keeps Ic within a few percent?" The honest answer needs numbers, so we will use one common set throughout: Vcc = 12 V, Rc = 3 kΩ, Vbe = 0.7 V, and a target of Ic of about 2 mA with Vce near 6 V.
Fixed bias: simple and fragile
Here a single resistor Rb runs from Vcc to the base. The base current is set by Ib = (Vcc - Vbe) / Rb and the collector current follows as Ic = beta × Ib. To hit 2 mA at beta = 100 you need Ib = 20 µA, so Rb = 11.3 V / 20 µA ≈ 565 kΩ.
Now swap in a part with beta = 200. Ib is unchanged at 20 µA, so Ic doubles to 4 mA. The drop across Rc becomes 12 V and Vce collapses to roughly zero: the transistor is saturated and the amplifier clips hard. Nothing in the circuit resists the change, so the stability factor S = dIc/dIb is simply beta. Add the temperature dependence of Icbo and Vbe and you also get thermal runaway risk. Fixed bias survives only in switches, where saturation is the goal.
Key fact: in fixed bias the Q-point current is proportional to beta, so a 2:1 spread in hFE becomes a 2:1 spread in Ic.
Collector-feedback bias: one loop of correction
Move the top of Rb from Vcc to the collector. If Ic rises, the collector voltage falls, which pulls the base current down and trims Ic back. That is negative feedback, and it costs one resistor. Writing the loop equation gives Ic ≈ beta × (Vcc - Vbe) / (Rb + (beta + 1) × Rc).
With Rb = 300 kΩ and Rc = 3 kΩ, beta = 100 gives Ic ≈ 1.87 mA and Vce ≈ 6.3 V. Beta = 200 gives Ic ≈ 2.50 mA and Vce ≈ 4.5 V. The current moved by about 33 percent instead of 100 percent, and the transistor stays comfortably in the active region. Notice the term (beta + 1) × Rc in the denominator: the larger it is relative to Rb, the more Ic becomes a function of the resistors alone, approaching (Vcc - Vbe) / Rc. The price is lower gain, because Rb also bridges output to input (Miller effect), so the small-signal gain and input impedance shrink.
Voltage-divider bias: let Re do the work
The four-resistor network, R1 and R2 forming a divider with Rc and an emitter resistor Re, is the workhorse. Thevenin-reduce the divider to Vth = Vcc × R2 / (R1 + R2) and Rth = R1 || R2. The emitter current is then Ie = (Vth - Vbe) / (Re + Rth / (beta + 1)).
Take R1 = 47 kΩ, R2 = 10 kΩ, Re = 1 kΩ, Rc = 3.3 kΩ. Vth = 2.1 V and Rth = 8.2 kΩ. At beta = 100, Ie = 1.405 V / (1000 + 81.6) ≈ 1.30 mA. At beta = 200, Ie = 1.405 V / (1000 + 41) ≈ 1.35 mA. Doubling beta moved the current by only about 4 percent. The mechanism is that the base is held by a nearly ideal voltage, so any extra Ic raises the emitter voltage and reduces Vbe, a local series-series feedback with a stability factor of about 1 + Rth/Re instead of beta.
Watching the Q-point drift
The animation below puts the fixed-bias circuit on its DC load line. As beta sweeps from 100 to 200 the Q-point slides from mid-supply straight into saturation, where no signal swing is left. Repeat the exercise with the divider and the dot barely moves.
Side-by-side comparison
| Scheme | Ic spread (beta 100 to 200) | Stability factor S | Cost and gain impact |
|---|---|---|---|
| Fixed bias | +100% | about beta | 1 resistor, full gain |
| Collector feedback | +33% | about 1 + Rb/Rc stage | 1 resistor, gain reduced by Miller effect |
| Divider + Re | +4% | about 1 + Rth/Re | 4 resistors, bypass Re with a capacitor to restore AC gain |
Key fact: a good rule is Rth ≤ (beta_min + 1) × Re / 10, with the divider current at least ten times Ib and about Vcc/10 dropped across Re.
Practical design rules and tooling
- Pick Re to drop 1 V or about a tenth of Vcc, so Vbe's -2 mV/°C drift is a small fraction of the voltage across Re.
- Choose divider current of 10 × Ib at beta_min, then compute R1 and R2 from Vth and Rth.
- Bypass Re with a capacitor whose reactance is below Re/10 at the lowest signal frequency, otherwise you lose gain.
- Verify with a Monte Carlo run: in Cadence Spectre or Synopsys HSPICE, sweep BF over 100 to 300 and temperature from -40 to 125 °C and check that Vce stays above about 1 V; Siemens (Mentor) Eldo and the free ngspice do the same job.
- In integrated design the same principle appears as a current mirror referenced to a bandgap, since resistor dividers and Re cost area and cannot match across process corners. Our common-emitter amplifier article shows how the bias point sets gain, and the current mirror guide covers the IC equivalent.
Teams that need this kind of bias analysis in a real product often bring in outside help; Avecas design services run corner and Monte Carlo sign-off on analog blocks.
Want to build and simulate these circuits yourself? Explore the analog tracks in CourseTron courses and practise biasing with guided SPICE labs.
Frequently asked questions
Which biasing method is best against beta variation?
Voltage-divider bias with an emitter resistor, because its Ic depends mainly on Vth, Vbe and Re rather than on beta.
Why does collector-feedback bias reduce but not remove beta sensitivity?
The feedback resistor senses only the collector voltage, and the term Rb/beta remains in the current equation, so a residual dependence stays unless Rb is small compared with beta × Rc.
Why not make the divider as stiff as possible?
Low-valued R1 and R2 waste power and load the signal source, so the design trades divider current against input impedance, typically choosing about ten times Ib.
Does the emitter resistor reduce AC gain?
Yes, unless it is bypassed by a capacitor; with the bypass the DC stability remains while the AC gain returns close to gm × Rc. See the common-emitter amplifier article for the gain derivation. For hands-on practice, ChipXpert VLSI training offers instructor-led analog design labs.