In short: A current mirror is an analog building block that copies a reference current into one or more output branches by forcing matched transistors to share the same gate-source (or base-emitter) voltage. The basic two-transistor version is simple but limited by channel-length modulation; the cascode mirror stacks a second device to raise output resistance and make the copy far more accurate.
A current mirror is a circuit that senses a known reference current and reproduces (mirrors) it at another node, ideally independent of the voltage at that node. It is one of the most reused structures in analog and mixed-signal IC design because currents, not resistors, are the natural way to bias and distribute signals on a chip.
The idea rests on a single fact about MOSFETs and BJTs: devices that are physically identical and biased with the same control voltage carry the same current. In a MOS mirror the diode-connected input transistor converts the reference current into a gate-source voltage, VGS. That voltage is shared with the output transistor, so the output copies the input — scaled by the ratio of their widths if you want a multiple.
In the diode-connected device M1, the drain is tied to the gate, so whatever current the reference pushes through it is accommodated by M1 settling to the VGS that satisfies its square-law relationship. Because M2's gate connects to the same node, it sees the identical VGS. If both transistors have equal width-to-length ratios and operate in saturation, IOUT ≈ IREF.
To obtain a scaled copy, you deliberately make M2 wider or narrower. A mirror ratio of 1:N simply means (W/L)2 = N × (W/L)1, producing IOUT ≈ N · IREF. This is how a single reference generator can bias dozens of branches with different magnitudes from one trimmed source.
An ideal current source has infinite output resistance: its current does not change no matter what voltage appears across it. A real MOSFET does not — its drain current rises slightly with drain-source voltage because of channel-length modulation, captured by the parameter λ. The small-signal output resistance of a single transistor is ro = 1/(λ·ID).
In a basic mirror, if the output node voltage differs from the reference node voltage, the two transistors do not have identical VDS, so the copy drifts. The output current depends on load voltage — a systematic error that worsens the lower the intrinsic gain of the process. For precise biasing or high-gain amplifier loads, a single ro is simply not enough.
The cascode mirror stacks a second transistor on top of each mirror device. The upper (cascode) transistor shields the lower one so its VDS stays nearly constant regardless of the output node swing. The result is a dramatic boost in output resistance — roughly Rout ≈ gm·ro·ro, the product of the cascode device's intrinsic gain and the lower device's ro.
That higher resistance means the mirrored current barely changes as the load voltage moves, so the copy is far more faithful. The trade-off is voltage headroom: a classic cascode needs two VDS,sat plus a threshold of stacking, eating into the available swing. Low-voltage designs use the wide-swing (low-voltage) cascode, which biases the cascode gates so each transistor sits just at the edge of saturation, recovering most of the headroom while keeping the high resistance.
On paper the copy is exact; on silicon it is only as good as the matching between devices. The main error sources are:
Designers fight these with deliberate layout: large device areas to average out random mismatch, common-centroid and interdigitated placement to cancel gradients, dummy devices at the edges, and generous overdrive where headroom allows. These techniques are why matching-critical mirrors look so symmetric in a real layout.
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Explore CourseTron Courses →A basic mirror uses two transistors and has output resistance equal to a single ro, so its copy drifts with load voltage. A cascode mirror stacks a second transistor per branch to hold VDS constant, raising output resistance to about gmro2 for a much more accurate, load-independent current.
The mirror relies on the saturation-region relationship between VGS and ID. If a device drops into the triode (linear) region, its current becomes strongly dependent on VDS and the copy collapses. Keeping enough headroom to stay in saturation is a core design constraint.
Scale the output transistor's width-to-length ratio. With (W/L)out = N·(W/L)ref, the output current is roughly N times the reference. For good matching, N is usually built from several unit devices in parallel rather than one odd-sized transistor.
Device mismatch (threshold and β variation), unequal drain-source voltages, and thermal or process gradients across the die. Larger areas, common-centroid layout and cascoding are the standard remedies.
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