In short: A common-emitter stage turns a small base-voltage change into a large, inverted collector-voltage change with gain of about –gm·(RC‖RL), a moderate input resistance (R1‖R2‖rπ), an output resistance close to RC, and coupling capacitors that pass the signal while keeping the DC bias intact.
Why the common-emitter stage matters
If you interview for an analog role, someone will hand you a single-transistor amplifier and ask for gain, input resistance and output resistance within two minutes. The common-emitter (CE) configuration is the workhorse behind that question: it is the only single-BJT stage that gives both voltage and current gain, which is why it shows up as the first gain stage in audio preamps, sensor front ends and the discrete building blocks behind op-amp internals.
The analysis has two halves. First you bias the transistor so it sits in the forward-active region (covered in BJT biasing techniques). Then you superimpose a small AC signal and study it with a linear small-signal model. Keeping those two worlds separate is the core skill, and the coupling capacitors are what make the separation physically possible.
The circuit and its DC operating point
Take VCC = 12 V, R1 = 47 kΩ, R2 = 10 kΩ, RC = 4.7 kΩ, RE = 1 kΩ and a transistor with β = 100. The Thevenin base voltage is 12 × 10/57 ≈ 2.1 V. Subtract VBE ≈ 0.7 V and you have about 1.4 V across RE, so IE ≈ 1.4 mA (the base current slightly loads the divider, so expect roughly 1.2 mA in practice). Take IC ≈ 1.2 mA: the collector sits near 12 – 1.2 mA × 4.7 kΩ ≈ 6.4 V, leaving VCE ≈ 4.2 V. That is comfortably mid-range, so the output can swing in both directions before clipping.
Key fact: at room temperature gm = IC/VT ≈ IC/26 mV. At 1.2 mA that is about 46 mS, and every gain number below is built from this single quantity.
Small-signal model and voltage gain
For AC analysis, short the supply and treat the capacitors as shorts. The transistor becomes a current source gm·vπ in parallel with ro, with rπ = β/gm between base and emitter. With gm = 46 mS and β = 100, rπ ≈ 2.2 kΩ. The collector current gm·vπ flows through RC in parallel with the load, so:
- Av = –gm · (RC ‖ RL ‖ ro)
- RC ‖ RL = 4.7k ‖ 10k ≈ 3.2 kΩ, so Av ≈ –46 mS × 3.2 kΩ ≈ –147
- Unloaded (RL removed) the gain rises to –216, a reminder that the next stage always steals gain.
Notice that gain depends on a current (through gm) and a resistor ratio, not on β. That is why a well-biased CE stage is predictable even when β varies by 3x across parts. The Early voltage matters only as a ceiling: with VA = 100 V, ro ≈ 83 kΩ at this current, which barely dents the result but limits the maximum gain of any CE stage to –VA/VT ≈ –3800.
Phase inversion: why the output flips
When vin rises, vBE rises, so IC rises exponentially. A larger IC drops more voltage across RC, so the collector voltage falls. The output therefore moves opposite to the input, a 180° shift at mid-band, and the minus sign in the gain formula is not decoration. This matters for feedback: a single CE stage in a closed loop already supplies an inversion, so a two-stage amplifier gives a non-inverting overall response and a three-stage ring oscillator can be built from three inverting stages.
Input and output impedance
Looking into the base, the signal sees R1 ‖ R2 ‖ rπ. Here 47k ‖ 10k ≈ 8.2 kΩ, in parallel with 2.2 kΩ, gives Rin ≈ 1.7 kΩ. That is low enough that a 10 kΩ source would lose most of its voltage before reaching the transistor: the attenuation is Rin/(Rs + Rin) ≈ 0.15. If you leave RE unbypassed, the resistance seen into the base rises to roughly rπ + (β+1)RE, about 100 kΩ here, trading gain for a much friendlier input.
At the output, looking back into the collector gives RC in parallel with ro, essentially RC = 4.7 kΩ. This is a moderately high output resistance, which is why a CE stage drives low-impedance loads badly and is usually followed by an emitter follower. The table summarises the two configurations.
| Quantity | CE with bypassed RE | CE with unbypassed RE |
|---|---|---|
| Voltage gain | ≈ –gm(RC‖RL) ≈ –147 | ≈ –(RC‖RL)/(re+RE) ≈ –3 |
| Rin | R1‖R2‖rπ ≈ 1.7 kΩ | R1‖R2‖[rπ+(β+1)RE] ≈ 7.6 kΩ |
| Rout | ≈ RC = 4.7 kΩ | ≈ RC = 4.7 kΩ |
| Gain sensitivity to temperature | High (via gm) | Low |
Key fact: the unbypassed gain is –(RC‖RL)/(re + RE) with re = 1/gm ≈ 22 Ω. Because RE dominates, the gain barely cares about temperature, β or device spread. That is degeneration, and it is the cheapest negative feedback you will ever apply.
The role of the coupling and bypass capacitors
C1 and C2 are DC blocks. Without C1, the signal source (often grounded at DC) would pull the base away from the 2.1 V that R1/R2 set, wrecking the bias. Without C2, the load would sink DC current from the collector and shift the output level. Each capacitor forms a high-pass filter with the resistance around it, giving a corner at fL = 1/(2π·R·C):
- C1 sees Rs + Rin. With Rs = 1 kΩ, Rin = 1.7 kΩ and C1 = 10 µF the corner is about 5.9 Hz.
- C2 sees RC + RL = 14.7 kΩ. With C2 = 1 µF, fL ≈ 11 Hz.
- CE sees about re ‖ RE ≈ 22 Ω, so even 100 µF only gets the corner to roughly 72 Hz, and this is often the dominant low-frequency pole. A common design rule is to set the bypass corner a decade below the lowest wanted frequency.
At the high end, the base-collector capacitance Cμ is multiplied by (1 + |Av|) by the Miller effect. At gain 147 a mere 2 pF becomes about 300 pF at the input, which with a 1 kΩ source gives a pole near 0.5 MHz. This gain-bandwidth trade-off is why designers reach for cascode stages in wide-band amplifiers.
Verifying it in simulation and practice
Hand analysis gets you to roughly 10-15% of reality, so close the loop with a simulator. In Cadence Spectre or Synopsys HSPICE, run a .op to confirm VCE and gm, an .ac sweep for gain and corner frequencies, and a .tran with a 10 mV sine to see inversion and clipping. Siemens (Mentor) Eldo gives equivalent runs for discrete and integrated designs. A frequent bench surprise is hum or distortion: if the input swing exceeds a few millivolts, the exponential I-V curve distorts the output because small-signal gain assumes vπ well below 10 mV. Teams doing production analog work, such as the design group at Avecas design services, apply exactly these checks before layout.
Once you can derive these numbers from memory, extend them to a two-stage amplifier and to the emitter-follower buffer covered in BJT emitter follower and buffering. For hands-on practice with guided labs, see our CourseTron courses, and for instructor-led career training explore ChipXpert VLSI training.
Ready to go beyond one transistor? Join the CourseTron Analog Design course for guided derivations, SPICE labs and interview drills.
Frequently asked questions
Why does a common-emitter amplifier invert the signal?
A rising base voltage increases collector current, which increases the drop across RC, so the collector voltage falls. The output moves opposite to the input, giving a 180° shift at mid-band frequencies.
What is the voltage gain of a CE stage with an unbypassed emitter resistor?
Approximately –RC/(re + RE), or –(RC‖RL)/(re + RE) with a load, where re = 1/gm. If RE is much larger than re, the gain is close to –RC/RE and nearly independent of the transistor.
Why add a bypass capacitor across RE?
RE stabilises the DC bias but also degenerates the AC gain. The bypass capacitor shorts RE at signal frequencies so the full gm gain is restored while the DC bias stability remains.
How do I choose the coupling capacitor values?
Compute the resistance each capacitor sees, then pick C so that 1/(2πRC) is at least a decade below the lowest frequency you need. Work out the bypass capacitor first, as it usually sees the smallest resistance and needs the largest value.