In short: The four classic VLSI design styles — full-custom, standard-cell, gate-array, and FPGA — trade engineering effort and NRE cost against performance, density, and time-to-market, so you pick the one whose economics match your volume and schedule, not the one with the best peak numbers.
Ask ten engineers "how is a chip designed?" and you will often hear a single answer: synthesis plus place-and-route. That is really only one of several design styles, each of which decides how much of the silicon you hand-craft versus how much you borrow from pre-built, pre-characterized building blocks. The choice happens before RTL is frozen and it governs everything downstream. This article walks through the four dominant styles and the trade-offs that steer the decision.
The fundamental trade: effort versus silicon efficiency
Every style sits on one axis: how much design freedom you keep. Keep full freedom and you place every transistor yourself — maximum performance and density, but maximum labour and schedule. Give up freedom to automated tools working from a library, and you trade a little performance for a 10–100x cut in engineering time. The art of VLSI planning is reading your volume, clock target, and power budget and landing on the right point of that curve.
Full-custom design
In full-custom, engineers draw transistor geometries and wiring by hand (or with lightly automated assist) to extract every picosecond and every square micron. This is how high-speed SRAM bit-cells, analog PLLs, SerDes lanes, and flagship CPU datapaths are built. A 6T SRAM cell laid out custom can be less than half the area of the same function assembled from logic-library cells, and the clocking can reach frequencies a synthesized block cannot.
The price is brutal: a complex full-custom block can take many engineer-months, and every process-node migration demands a re-layout. Tools here are schematic-and-layout driven — Cadence Virtuoso for schematic/layout, Spectre for circuit simulation, and sign-off DRC/LVS with Siemens Calibre.
Key fact: Full-custom can cut memory bit-cell area by 40–60% versus a synthesized equivalent, which is exactly why even an otherwise standard-cell SoC still drops in a hand-crafted SRAM compiler macro.
Standard-cell (semi-custom) design
This is the workhorse of modern digital SoCs. A foundry or IP vendor pre-designs and characterizes a library of a few hundred logic cells — inverters, NANDs, flip-flops, each in several drive strengths. You write RTL, a synthesis tool (Synopsys Design Compiler / Fusion Compiler or Cadence Genus) maps it to those cells, and a place-and-route tool (Cadence Innovus or Synopsys IC Compiler II) arranges and wires them on fixed-height rows. Because the cells are pre-verified and the flow is automated, a multi-million-gate block goes from RTL to GDSII in weeks rather than years.
Density and speed are very good — within roughly 2–3x of full-custom for random logic — while design effort collapses. The flow is the backbone of the standard VLSI design flow, and timing closure, clock-tree synthesis, and DFT insertion all plug into it. For hands-on practice with real libraries and sign-off, design-services teams such as Avecas VLSI design services run production standard-cell flows daily.
Gate-array and structured ASIC
Gate-array sits between standard-cell and full-custom in a different way: the silicon vendor pre-fabricates wafers of identical transistor "sea-of-gates" up to the contact layer, and your design only customizes the metal interconnect masks. Because the expensive base layers are shared across many customers, mask (NRE) cost and turnaround drop sharply. Structured ASICs (the modern descendant) pre-place memories and I/O too, customizing only a couple of metal layers.
The catch is utilization: you can only use the gates the array gives you, so density and achievable frequency lag standard-cell, and leftover transistors are wasted. Gate-arrays occupy a shrinking but real niche for low-to-mid volumes where full mask-set NRE cannot be justified.
FPGA
An FPGA is the ultimate "give up silicon efficiency for flexibility" style: the device is fully fabricated, and you configure a fabric of look-up tables (LUTs), flip-flops, DSP slices, and block RAM by loading a bitstream. There are no masks, no NRE, and you can reprogram the same chip after a bug — turnaround is a compile, not a tape-out. AMD/Xilinx Vivado and Intel/Altera Quartus drive the flow.
Because logic is emulated on a generic fabric, an FPGA typically runs 3–4x slower, draws far more dynamic power, and costs much more per unit than the equivalent ASIC at volume. That is why FPGAs dominate prototyping, low-volume systems, and reconfigurable products, while a design that ships in millions of units migrates to standard-cell.
Side-by-side trade-offs
| Style | Design effort / NRE | Performance | Density | Unit cost @ volume | Best for |
|---|---|---|---|---|---|
| Full-custom | Very high | Highest | Highest | Low | SRAM, analog, flagship datapaths |
| Standard-cell | Moderate | High | High | Low | Most digital SoCs |
| Gate-array | Low–moderate | Medium | Medium | Medium | Low/mid-volume ASICs |
| FPGA | Lowest | Lower | Lowest | Highest | Prototyping, low volume, reconfig |
Key fact: Real chips mix styles. A typical SoC is standard-cell logic, full-custom SRAM compiler macros and PLLs, and hardened I/O — the "design style" is a per-block decision, not one choice for the whole die.
If you want to see where each style lands in a real tape-out, the companion piece on the end-to-end VLSI design flow and the deep-dive on standard-cell library characterization show how these decisions ripple through synthesis and sign-off.
Want to build these flows hands-on? CourseTron's physical-design and VLSI tracks take you from RTL through Innovus place-and-route on real libraries. Explore the full catalogue on our courses page and start where your gaps are.
Frequently asked questions
Is standard-cell the same as ASIC?
Not exactly. ASIC (Application-Specific Integrated Circuit) is the product category; standard-cell, full-custom, and gate-array are design styles used to build an ASIC. Most ASICs today are predominantly standard-cell with some full-custom blocks.
Why not always use FPGAs if they are reprogrammable?
At high volume the per-unit cost, power draw, and speed penalty of FPGAs dominate. A product shipping in millions of units saves far more than the mask NRE by migrating to a standard-cell ASIC.
Where is full-custom still mandatory?
Analog and mixed-signal blocks (PLLs, ADCs, SerDes), high-density memory bit-cells, and the most aggressive high-frequency datapaths, where synthesized cells cannot meet the area, speed, or noise targets.
What tools should a beginner learn first?
Start with a standard-cell RTL-to-GDSII flow — Synopsys Design Compiler or Cadence Genus for synthesis, and Cadence Innovus or Synopsys ICC2 for place-and-route — because that covers the vast majority of digital design work.