ASIC design flow

In short: ASIC design turns a product idea into a fabricated chip through a flow (spec → RTL → verification → synthesis → place-and-route → signoff → tapeout), and the choice between full-custom, standard-cell (semi-custom), and gate-array styles is really a trade of engineering effort and NRE cost against silicon area, performance, and time-to-market.

What an ASIC actually is

An Application-Specific Integrated Circuit is a chip built for one job, as opposed to a general-purpose FPGA or microprocessor. A smartphone's power-management IC, a crypto-mining hashing engine, and the display driver in your TV are all ASICs. Because the function is fixed in silicon, an ASIC can hit power, area, and clock-frequency targets an FPGA cannot reach — a 7 nm ASIC routinely runs 2–3× faster than the same logic on a comparable FPGA while using a fraction of the energy per operation. The cost of that win is a long, unforgiving design flow and large up-front spending.

The three design styles

"ASIC" is an umbrella. The real decision is how much of the chip you hand-craft:

Full-custom gives absolute control: a memory designer sizes individual NMOS/PMOS devices to pack a 6-transistor SRAM cell into the smallest possible footprint, or to squeeze picoseconds out of a critical PLL. It is slow and expensive, so it is reserved for the few blocks where it pays off.

Standard-cell is how almost all digital logic is built today. A foundry (TSMC, Samsung, GlobalFoundries, Intel) and its library partners supply a cell library of pre-designed, pre-characterized gates — INV, NAND, flip-flops, adders — each with timing, power, and physical views. Your RTL is synthesized onto those cells automatically. You trade a little area and speed for enormous productivity: a team can take a million-gate block from RTL to layout in weeks.

Gate-array (and its modern cousin, structured ASIC) pre-fabricates wafers of uncommitted transistors and only customizes the top metal layers per design. Because the expensive base layers are shared, mask cost drops sharply — attractive for prototypes or parts shipping in the thousands rather than millions.

Key fact: A full mask set at an advanced node (5 nm) can cost well over US$10 million. That single number explains why standard-cell flows dominate and why engineers obsess over getting first silicon right.

NRE: why volume decides everything

Non-Recurring Engineering cost is everything you pay once before a single sellable chip exists: EDA tool licenses, engineering salaries, IP licensing, and above all the photomask set. Per-chip cost, by contrast, is silicon area plus packaging and test. The economics are simple:

• High NRE, low per-unit cost (ASIC) wins at high volume.
• Zero NRE, high per-unit cost (FPGA) wins at low volume.

The crossover is often around 10,000–100,000 units depending on complexity. If a US$4 million NRE is amortized over 1 million chips, it adds US$4 each; over 10,000 chips it adds US$400 — which can dwarf the die cost itself.

The end-to-end standard-cell flow

A modern digital ASIC moves through a well-defined pipeline. The industry shorthand is "RTL to GDS." Each stage has dominant EDA tools:

• Specification & architecture — define function, interfaces, power/area/speed (PPA) budgets.
• RTL design — write behavior in Verilog/SystemVerilog or VHDL.
• Functional verification — simulation (Synopsys VCS, Cadence Xcelium, Siemens Questa), UVM testbenches, and formal checks. This consumes 50–70% of total engineering effort.
• Logic synthesis — map RTL to standard cells against timing constraints (Synopsys Design Compiler / Fusion Compiler, Cadence Genus), producing a gate-level netlist.
• DFT insertion — add scan chains and BIST so the fabricated die can be tested.
• Place-and-route — floorplan, place cells, build the clock tree, route metal (Cadence Innovus, Synopsys IC Compiler II).
• Signoff — static timing analysis (Synopsys PrimeTime), power, and physical verification: DRC and LVS (Siemens Calibre).
• Tapeout — ship the final GDSII layout to the foundry for mask making.

We cover the hand-off from logic to physical design in depth in our guide to the VLSI design flow from RTL to GDS, and the verification side in ASIC functional verification with UVM.

Watch a bit propagate through the flow

The animation below shows a logic value being launched from one flip-flop, settling through a cloud of combinational standard cells, and being captured at the next clock edge — the core timing event that static timing analysis must prove meets setup and hold at every node.

Key fact: At signoff, a single timing path is checked across dozens of PVT corners (process, voltage, temperature) and multiple modes. A large SoC can have billions of timing paths — which is why STA tools and multi-corner analysis are non-negotiable.

Avecas and partners run exactly this industrial flow on real foundry PDKs; if you need a design-services team rather than a course, see Avecas VLSI design services.

Choosing a style in practice

For a startup building a 100k-unit IoT sensor hub, a standard-cell flow on a mature 28 nm or 22 nm node balances NRE against unit cost beautifully. A hyperscaler building an AI accelerator for millions of units at 3 nm will spend tens of millions on NRE but still win on per-unit economics and power. A defense prototype needing 500 parts in six months may pick a structured ASIC to slash mask cost. The flow is the same; only the style and node change.

Ready to run the full RTL-to-GDS flow on real EDA tools and foundry PDKs? CourseTron's VLSI Physical Design track takes you from Verilog to a signed-off GDSII with hands-on labs. Explore our courses →

Frequently asked questions

Is an FPGA an ASIC?

No. An FPGA is a reconfigurable, general-purpose device you program after manufacture; an ASIC's function is permanently fixed in silicon. FPGAs have near-zero NRE but higher per-unit cost, power, and lower speed, making them ideal for prototyping and low volumes.

What is the difference between full-custom and semi-custom?

Full-custom means hand-designing individual transistors for maximum density and speed. Semi-custom (standard-cell) means assembling your design from a foundry's library of pre-made, pre-characterized logic gates, which is far faster to design but slightly larger and slower.

Why is ASIC NRE so expensive?

The dominant cost is the photomask set used to pattern each layer on the wafer, which at advanced nodes exceeds several million dollars. Add EDA licenses, IP, and engineering time, and total NRE can reach tens of millions before a single chip is sold.

What does "tapeout" mean?

Tapeout is the milestone where the final, verified GDSII layout is sent to the foundry to manufacture masks and fabricate wafers. The name is historical, from when layout data was delivered on magnetic tape.