In short: A CMOS gate pairs a PMOS pull-up network that drives the output high with a complementary NMOS pull-down network that drives it low, so exactly one network conducts for any input and the gate draws almost no static current.
Complementary Metal-Oxide-Semiconductor (CMOS) logic is the foundation of virtually every digital chip shipped today, from a 28 nm microcontroller to a 3 nm GPU. The elegance of CMOS is a single structural idea repeated billions of times: build two transistor networks that are logical complements of each other, wire one to the supply and one to ground, and let them fight over a shared output node. Understanding that duality is the difference between memorising gate symbols and actually reasoning about power, delay, and robustness in silicon.
The Two-Network Principle
Every static CMOS gate is composed of two parts connected to a common output node:
- Pull-Up Network (PUN): built entirely from PMOS transistors, connected between VDD and the output. A PMOS conducts when its gate is at logic
0. - Pull-Down Network (PDN): built entirely from NMOS transistors, connected between the output and ground. An NMOS conducts when its gate is at logic
1.
The two networks are duals: wherever the PDN uses transistors in series, the PUN uses them in parallel, and vice versa. This is enforced by De Morgan's laws. If the PDN implements the condition under which the output is pulled to 0, the PUN automatically implements its complement, pulling the output to 1 for every other input combination.
Why it matters: Because the PUN and PDN are complementary, for any valid static input exactly one network conducts. There is never a direct DC path from VDD to ground, which is why static CMOS burns essentially zero current between switching events — only leakage (sub-threshold, gate, and junction) remains.
The Inverter: CMOS in Miniature
The inverter is the simplest gate and the template for everything else. It uses one PMOS and one NMOS, their gates tied together to the input. When A = 0, the PMOS turns on and the NMOS turns off, so the output is pulled to VDD (1). When A = 1, the roles swap and the output is pulled to ground (0). The output is a clean, rail-to-rail inversion with no resistive divider, unlike older NMOS-only or pseudo-NMOS logic where a static pull-up resistor wastes power and degrades the 0 level.
NAND and NOR: Series vs Parallel
A 2-input NAND pulls its output low only when both inputs are high, so its PDN is two NMOS devices in series. By duality the PUN is two PMOS devices in parallel — either input being low is enough to pull the output high.
A 2-input NOR is the mirror image: the PDN has two NMOS in parallel (either input high pulls low), and the PUN has two PMOS in series (both inputs must be low to pull high).
| Gate | PDN (NMOS) | PUN (PMOS) | Function |
|---|---|---|---|
| Inverter | 1 device | 1 device | OUT = Ā |
| 2-input NAND | 2 in series | 2 in parallel | OUT = (A·B)' |
| 2-input NOR | 2 in parallel | 2 in series | OUT = (A+B)' |
Sizing consequence: Series transistors stack their resistance. A NOR stacks PMOS in series, and because holes have roughly 2–3× lower mobility than electrons, those PMOS must be made very wide to match pull-down speed. This is exactly why experienced designers prefer NAND-based structures: the NAND stacks the faster NMOS, keeping the slow PMOS in parallel. Standard-cell libraries from vendors reflect this — NAND2 is almost always smaller and faster than NOR2 at the same drive strength.
Switching Behaviour and the Transient Spike
The "zero static current" claim has one caveat worth internalising for timing and power sign-off. During a transition, as the input sweeps through the threshold region, there is a brief window where both networks conduct simultaneously. This produces a short crowbar or short-circuit current, plus the charge/discharge of the load capacitance (the dynamic C·V²·f component that dominates active power). In a modern design flow you quantify this with a tool like Synopsys PrimeTime PX or Cadence Voltus, driven by cell power models characterised in Liberty (.lib) files.
Noise Margins and the Voltage Transfer Curve
Because CMOS swings rail to rail and has a high-gain transition region, its noise margins are excellent — typically around 40% of VDD for each of NMH and NML in a well-sized gate. The switching threshold VM, where input equals output, can be tuned by the PMOS/NMOS width ratio; a ratio near 2:1 (P:N) centres VM at VDD/2 in older nodes. This robustness is a key reason CMOS displaced earlier families; for a deeper comparison of logic families see our companion article on CMOS vs TTL.
Beyond Static Gates
The complementary structure generalises to any Boolean function: express the complement of the function as a product-of-sums or sum-of-products, map it to the PDN, and let duality generate the PUN. Complex gates like AOI (AND-OR-INVERT) and OAI combine series/parallel stacks to implement multi-level logic in a single gate, saving area and delay versus cascading primitives. When you move to sequential elements and clocking, the same transistor pairs reappear inside flip-flops and transmission gates — a topic we cover in MOSFET operating regions. For a structured path through all of this, start with our VLSI course catalogue.
Teams building real tape-outs lean on characterised standard-cell libraries and sign-off tools; if you want hands-on exposure to industrial flows, the physical-design training at ChipXpert's VLSI programs walks through synthesis-to-GDS using the same gate primitives discussed here.
Ready to go from gate theory to building real standard cells and running SPICE on them? Enrol in CourseTron's Digital VLSI Design track and design, size, and simulate your own CMOS library.
Frequently Asked Questions
Why are CMOS gates naturally inverting?
Because a conducting PMOS passes VDD and a conducting NMOS passes ground, the only way to get a clean output is to let the pull-up assert 1 and the pull-down assert 0. The result is always the complement of the input condition, so basic static CMOS gates (NAND, NOR, inverter, AOI) are inverting. Non-inverting gates like AND and OR are built by adding an inverter stage.
Why is a CMOS NAND preferred over a NOR?
A NAND stacks NMOS transistors in series in its pull-down path, and NMOS are intrinsically faster due to higher electron mobility. A NOR stacks slow PMOS in series in its pull-up path, forcing large widths to meet timing. For equal performance, NAND cells are smaller and lower-power, so synthesis tools favour NAND-dominated netlists.
Does static CMOS really consume no power?
No static DC power to speak of between transitions — only leakage. But every switching event dissipates dynamic power (charging/discharging load capacitance) plus a small short-circuit current. At advanced nodes leakage becomes significant, which is why power-gating and multi-Vt cells are used.
How do I build a gate for an arbitrary Boolean function?
Write the function's complement, implement it in the NMOS pull-down network (AND → series, OR → parallel), then create the dual network in PMOS for the pull-up (series ↔ parallel swapped). The two networks together form a single complex gate.