In short: Low-power VLSI design cuts both dynamic power (switching and short-circuit, which scales with C·V²·f) and static power (leakage) using a coordinated set of techniques — clock gating, power gating, voltage/frequency scaling, and multi-Vt cell libraries — applied through the RTL-to-GDSII flow and verified against a UPF/CPF power intent spec.
Power, not raw timing, is the binding constraint for most modern chips. A mobile SoC must live inside a few watts so the package does not cook and the battery lasts a day; a data-centre accelerator is limited by what the rack can cool. Below we survey where the power actually goes and the main techniques engineers use to claw it back, with the kinds of numbers and tools you are expected to know in an interview.
Where the power goes: dynamic vs. static
Total power in a CMOS circuit splits into two families. Dynamic power is consumed only when nodes toggle, and is dominated by charging and discharging load capacitance:
Pdyn = α · C · VDD² · f
Here α is the activity factor (fraction of clocks on which a node switches), C the switched capacitance, VDD the supply, and f the frequency. The square on VDD is the single most important fact in low-power design: dropping the supply from 1.0 V to 0.8 V cuts dynamic power by roughly 36% for the same switching. A smaller, usually secondary dynamic term is short-circuit power, drawn during the brief window when both the pull-up and pull-down networks of a gate conduct as an input transitions; keeping input slews sharp keeps it small.
Static power is burned continuously, even when the clock is stopped, and is dominated by leakage — mainly sub-threshold conduction (current flowing through a transistor that is nominally "off") and gate-oxide tunnelling. Leakage was negligible at 180 nm but became first-order at 90 nm and below, and it rises sharply with temperature and with lower threshold voltage (Vt).
Rule of thumb: sub-threshold leakage roughly 10× for every ~60–100 mV drop in Vt (and climbs steeply with temperature). That exponential sensitivity is exactly why multi-Vt libraries exist.
Clock gating: kill the activity factor
The clock network is typically the busiest, highest-capacitance net on the die and can account for 30–50% of dynamic power on its own, because registers toggle their clock pin every cycle whether or not the data changes. Clock gating inserts an AND/latch-based integrated clock-gating (ICG) cell so a bank of flip-flops receives no edge when it is idle, driving α toward zero for that region.
Synthesis tools insert this automatically: Synopsys Design Compiler (set_clock_gating_style) and Cadence Genus will fold enable logic into ICG cells, often gating any register that has a feedback-mux enable. A latch in the gating cell suppresses glitches on the enable so the gated clock stays clean. The win is essentially free — it adds a little area and is functionally transparent — which is why it is the first lever every design pulls.
Power gating: attack leakage directly
Clock gating stops toggling but the gated block still leaks. Power gating physically disconnects an idle block from the supply rail using header (PMOS) or footer (NMOS) sleep transistors, collapsing a "virtual VDD/VSS" and cutting leakage by one to two orders of magnitude. It is more invasive than clock gating and brings its own overhead: isolation cells clamp the dangling outputs to a known value so powered-on neighbours do not see floating inputs; retention flip-flops save critical state on a small always-on rail; and a power-switch network must be sized and sequenced (a staged turn-on avoids inrush current that would crash the rail). Wake-up latency — typically microseconds — means power gating pays off only for blocks idle long enough to amortise it.
Voltage and frequency scaling
Because dynamic power scales with VDD², lowering the supply is the highest-leverage knob. Dynamic Voltage and Frequency Scaling (DVFS) runs each domain at the lowest (V, f) pair that still meets the current workload: a CPU might sit at 0.7 V / 800 MHz when idle and jump to 1.0 V / 2 GHz under load. Multi-voltage designs split the chip into separate power domains, requiring level shifters wherever a signal crosses from a lower to a higher voltage. A related idea, Adaptive Voltage Scaling, uses on-die process/temperature monitors to trim the supply to the minimum each individual die needs, recovering margin left on the table by worst-case corner sign-off.
Multi-Vt cell libraries
Foundries ship the same logic cell in two or three threshold flavours — High-Vt (HVT), Standard-Vt (SVT) and Low-Vt (LVT) — that trade speed against leakage. The tool's job is to use fast, leaky LVT cells only on paths that actually need the speed, and fill the rest of the design with low-leakage HVT cells. This is a leakage-recovery pass that Innovus, Fusion Compiler and Genus run after timing closure: every cell not on a critical path is swapped to a higher-Vt equivalent as long as slack permits.
| Cell flavour | Delay | Leakage | Use on |
|---|---|---|---|
| LVT (low Vt) | Fastest | Highest (~10×) | Critical paths only |
| SVT (standard) | Medium | Medium | General logic |
| HVT (high Vt) | Slowest | Lowest | Non-critical / most of die |
In practice a well-tuned block ends up 70–90% HVT/SVT cells, with LVT reserved for the handful of paths limiting Fmax — often cutting leakage by 2–5× at near-zero timing cost.
Tying it together: power intent and the flow
These techniques are not ad-hoc edits; they are declared once in a power intent file — IEEE 1801 UPF (Synopsys/Siemens) or Cadence CPF — that names the power domains, supply nets, isolation and level-shifter strategies, and retention registers. The same file drives synthesis, place-and-route and verification, so logic-equivalence and low-power rule checks (e.g. Synopsys VC LP, Siemens Questa) can confirm that every domain crossing has the right isolation and shifter before tape-out. This hooks directly into the broader VLSI design flow, and the physical side — inserting ICG cells, power switches and well taps — is covered in our physical design and place-and-route guide. Teams building full low-power silicon, from RTL power modelling to sign-off, often lean on specialist partners such as Avecas VLSI design services.
Want to practise this hands-on? CourseTron's low-power VLSI track walks you through writing UPF, inserting clock and power gating in Genus/Innovus, and running a leakage-recovery pass on a real block. Browse the full course catalogue to get started.
Frequently asked questions
Is clock gating or power gating more effective?
They target different components. Clock gating removes dynamic (switching) power and is cheap and automatic, so apply it everywhere. Power gating removes static (leakage) power but adds isolation cells, retention flops and wake-up latency, so reserve it for blocks that stay idle long enough to amortise the overhead.
Why is VDD the most powerful knob?
Dynamic power scales with the square of the supply, so a 20% voltage cut yields roughly a 36% dynamic-power reduction. Frequency must usually drop with it (a lower supply slows the transistors), which is why DVFS pairs the two.
What is the downside of low-Vt cells?
Low-Vt cells switch faster because the threshold is closer to zero, but sub-threshold leakage rises roughly an order of magnitude per threshold step, so a design full of LVT cells leaks heavily. Tools use them sparingly, only on timing-critical paths.
What does UPF actually do?
UPF (IEEE 1801) captures power intent — domains, supplies, isolation, level shifters, retention — separately from the RTL, so one specification drives synthesis, implementation and low-power verification consistently across the flow.