In short: The CMOS inverter uses one PMOS pull-up and one NMOS pull-down so that only one transistor conducts in steady state, giving rail-to-rail output, near-zero static current, and a sharp voltage transfer curve whose switching threshold and noise margins define every logic gate built on top of it.
If you understand the CMOS inverter completely, you understand roughly 80% of digital VLSI. Every NAND, NOR, flip-flop, and standard cell in a library like TSMC's 7nm or SkyWater 130nm is a structural generalization of this two-transistor circuit. This article walks through how it works, why it is efficient, and the three numbers interviewers always probe: the switching threshold, the noise margins, and the short-circuit current.
The circuit: complementary pull-up and pull-down
A CMOS inverter is a PMOS transistor whose source ties to VDD stacked above an NMOS transistor whose source ties to ground. Both gates connect to the input; both drains connect to the output. The word complementary is the whole trick: PMOS turns on with a low gate voltage, NMOS turns on with a high gate voltage, so for any static input exactly one device is strongly on and the other is off.
When Vin = 0, the NMOS gate-source voltage is 0 (off) while the PMOS sees VGS = -VDD (on). The output is pulled up to a clean VDD. When Vin = VDD, the roles swap and the output is pulled to a clean 0. There is no resistive divider holding the output at an intermediate level, which is exactly why CMOS beat the older NMOS-only (pseudo-NMOS) logic that burned static power through a resistive load.
Static power ≈ 0. In either stable state one transistor is off, so the only current is sub-threshold leakage — picoamps per gate in older nodes, though leakage grows sharply below 28nm and is a first-order design concern at 7nm and 5nm.
The voltage transfer characteristic (VTC)
Sweep Vin from 0 to VDD and plot Vout: you get the S-shaped VTC. It has five regions as the devices move through cutoff, saturation, and triode. The crucial feature is the steep middle region where small input changes produce large output swings — that high gain is what lets logic restore a degraded signal back to a full rail.
Switching threshold Vm
The switching threshold is the input voltage where Vin = Vout, found by equating the saturation currents of both devices. For long-channel devices it reduces to a ratio of transconductance parameters and threshold voltages. The designer's lever is the ratio of PMOS width to NMOS width.
Why PMOS is wider. Hole mobility is roughly 2–3× lower than electron mobility, so to centre Vm at VDD/2 you size (W/L)p ≈ 2–3 × (W/L)n. In a standard-cell library this fixed β-ratio is baked into every cell's layout.
A symmetric Vm = VDD/2 maximizes noise immunity and equalizes rise/fall delay. Skewing Vm higher or lower is a legitimate technique for timing-critical paths where one edge matters more than the other.
Noise margins
Noise margins quantify how much spurious voltage a gate can tolerate on its input and still interpret the logic level correctly. They are defined from the two unity-gain points on the VTC (where slope = -1):
| Quantity | Meaning | Formula |
|---|---|---|
| VIL | Max input still read as logic 0 | lower unity-gain point |
| VIH | Min input still read as logic 1 | upper unity-gain point |
| NML | Low noise margin | VIL − VOL |
| NMH | High noise margin | VOH − VIH |
Because CMOS drives VOL essentially to 0 and VOH essentially to VDD, its noise margins are large — typically around 0.4·VDD each for a symmetric gate. That robustness, combined with the restoring gain, is why you can chain thousands of gates without signal degradation accumulating.
The transient: short-circuit and dynamic current
During a switching transient there is a brief window where Vin sits between VTn and VDD−|VTp| and both transistors conduct, creating a direct path from VDD to ground. This short-circuit (crowbar) current is a real but usually secondary power component; keeping input edges sharp minimizes it. The dominant dynamic power is the C·VDD²·f switching of the output load capacitance — the single biggest reason the industry drives VDD down node after node.
SPICE-class simulators — Synopsys HSPICE, Cadence Spectre, or Siemens EDA's Eldo — are what engineers actually use to extract Vm, the noise margins, and propagation delay from a sized inverter against real foundry models before signing off a standard cell.
Where it leads
Generalize the single pull-down into a series/parallel NMOS network and the single pull-up into its complementary PMOS network and you get every static gate. A closely related building block that reuses the same complementary idea for a different purpose is the transmission gate, and the delay behavior you tune here is formalized in our note on propagation delay and logical effort. For a guided path through all of this, see our full VLSI course catalog. Teams needing hands-on tapeout mentoring often pair self-study with structured programs from ChipXpert's VLSI training.
Ready to design and simulate your own standard cells in an industry SPICE flow? Join the CourseTron Digital VLSI & Standard-Cell Design track and build a characterized inverter from schematic to layout.
Frequently asked questions
Why does CMOS consume almost no static power?
In both stable logic states one of the two transistors is fully off, breaking the DC path from VDD to ground. Only tiny sub-threshold leakage flows, so static power is near zero — unlike pseudo-NMOS which holds a resistive load current.
What sets the switching threshold Vm?
Vm is where Vin = Vout, set mainly by the ratio of PMOS to NMOS drive strength and their threshold voltages. Making the PMOS 2–3× wider compensates for lower hole mobility and centres Vm at VDD/2.
Why is the PMOS transistor wider than the NMOS?
Electrons move faster than holes, so an NMOS of a given width drives more current than an equal-width PMOS. Widening the PMOS equalizes pull-up and pull-down strength, balancing rise and fall times and symmetrizing the VTC.
What are noise margins and why do they matter?
Noise margins (NML and NMH) are the voltage slack between what a driver outputs and what a receiver still interprets correctly. Large CMOS noise margins let signals survive crosstalk, IR drop, and coupling across long gate chains.