In short: A transmission gate is a parallel NMOS + PMOS switch driven by complementary gate signals, so it passes both a strong logic 1 and a strong logic 0 with full rail-to-rail swing — fixing the degraded output that a lone pass transistor produces.
If you have ever built a 2-to-1 multiplexer, a static latch, or a bidirectional bus driver in a custom CMOS design, you have almost certainly reached for a transmission gate (TG). It is one of the most quietly important primitives in the VLSI toolbox: a voltage-controlled analog-style switch that lives inside digital flows. This article explains what the transmission gate is, why pairing an NMOS with a PMOS matters at the device-physics level, and where you will meet it in real silicon.
Why a single pass transistor is not enough
Start with a single NMOS used as a switch — classic pass-transistor logic. Drive the gate to VDD and try to pass a logic 1 from source to drain. The transistor conducts only while VGS > VTH. As the output node charges up, VGS shrinks, and conduction stops once the output reaches VDD − VTH. The node never reaches the rail. With a typical VTH of 0.4 V and a 1.0 V supply, your "high" is stuck around 0.6 V — a weak 1. NMOS is excellent at passing a strong 0 but poor at a strong 1.
A PMOS has the mirror-image problem: it passes a strong 1 but a degraded 0 (it stalls at |VTP| above ground). The engineering insight behind the transmission gate is simple and elegant: wire the two in parallel so each device covers the other's weakness.
⚡ Key fact: An NMOS passes a strong 0 and weak 1; a PMOS passes a strong 1 and weak 0. In parallel with complementary gates, at least one device is always in strong conduction across the entire 0-to-VDD range — giving full-swing transfer.
The transmission gate structure
A transmission gate places an NMOS and a PMOS source-to-source and drain-to-drain. The NMOS gate is driven by the control signal EN, and the PMOS gate by its complement EN'. When EN = 1 (so EN' = 0), both transistors turn on and the gate is a closed switch with a low on-resistance. When EN = 0, both turn off and the path is high-impedance (Hi-Z).
On-resistance: the reason both devices matter
The real payoff of the parallel structure shows up in the equivalent on-resistance Ron. Each device's channel resistance varies with the output voltage, but because they conduct in parallel, the total conductance is their sum. As the output sweeps from 0 to VDD:
- Near 0 V, the NMOS has a large VGS overdrive and dominates — low resistance.
- Near VDD, the PMOS has a large overdrive and dominates — low resistance.
- In the middle, both contribute, keeping the combined Ron relatively flat.
That flat, roughly constant Ron (often a few hundred ohms to a couple of kΩ depending on sizing and node) is why transmission gates make good analog switches and well-behaved digital pass elements. The animation below shows the output node charging to the full rail — contrast it mentally with an NMOS that would freeze at VDD − VTH.
Transmission gate vs. pass transistor at a glance
| Property | Single pass transistor | Transmission gate |
|---|---|---|
| Devices | 1 (NMOS or PMOS) | 2 (NMOS + PMOS) |
| Output high level | VDD − VTH (NMOS) | Full VDD |
| Output low level | Ground (NMOS) | Full ground |
| Control signals | 1 | 2 (needs the complement) |
| Area / routing | Smaller | Larger + inverter for EN' |
| Ron vs. Vout | Strongly varying | Nearly flat |
? Key fact: The cost of a transmission gate over a single pass transistor is a second device and an inverter to generate EN'. Many libraries fold that inverter in, which is why a standard-cell MUX2 cell is compact despite using TGs internally.
Where transmission gates show up in real designs
- 2:1 multiplexers. Two transmission gates, enabled by
SandS', select between two inputs with a single logic level of delay — faster and smaller than an AND-OR-INV equivalent in many standard-cell libraries. - Latches and flip-flops. A classic transmission-gate D-latch uses one TG for the transparent path and a second in the feedback loop to hold state. Almost every TG-based flop in a Synopsys DesignWare or TSMC standard-cell library is built this way.
- XOR/XNOR gates. A compact 2-transistor-plus-TG XOR is a staple of arithmetic datapaths and is far smaller than the full static-CMOS 12-transistor version.
- Bidirectional I/O and bus switches. Because a TG conducts in both directions and is symmetric, it works as a true bilateral switch — useful in analog muxes and sample-and-hold front ends.
In a modern implementation flow you rarely instantiate raw transistors: you let Cadence Genus or Synopsys Design Compiler map to library cells, and Innovus or Fusion Compiler place and route them. Verification tools like Siemens Calibre run LVS to confirm the TG topology matches your netlist, and SPICE (Synopsys HSPICE or Cadence Spectre) characterizes the Ron and charge-transfer behaviour you rely on. If you want to go deeper on building these cells and flows hands-on, ChipXpert's VLSI training walks through custom-cell design from schematic to layout.
Design cautions
Transmission gates are not free lunch. A few things catch newcomers:
- No restoring drive. A TG is just a switch; it does not amplify. Chain several in series and the Ron·C delay compounds quadratically. Insert a buffer every one or two stages.
- Charge sharing and leakage. When off, a TG is high-impedance, so dynamic nodes can droop. Keeper devices or static feedback are needed to hold state.
- Need for the complement. You must route both
ENandEN', and skew between them creates a brief shoot-through or glitch window.
For a broader treatment of how switch-logic families compare on area, delay, and robustness, see our companion guide on CMOS logic families, and browse the full curriculum on the CourseTron courses page.
Want to master pass-switch logic, standard-cell design, and full custom layout? Enroll in CourseTron's VLSI Design track and build real transmission-gate MUXes and latches in a live SPICE + layout lab. Explore the VLSI course →
Frequently asked questions
Why does a transmission gate need both NMOS and PMOS?
Because each transistor type only passes one logic level well. NMOS gives a strong 0 but a weak 1 (stuck at VDD − VTH), and PMOS gives a strong 1 but a weak 0. Combining them in parallel means at least one device is always strongly conducting, so the output swings fully from rail to rail.
Is a transmission gate the same as a pass transistor?
No. A pass transistor is a single MOSFET switch and produces degraded (threshold-dropped) output levels. A transmission gate is two MOSFETs in parallel with complementary gate drive, giving full-swing transfer and nearly constant on-resistance at the cost of extra area and a second control signal.
Can a transmission gate pass analog signals?
Yes. Because it is a bidirectional switch with a relatively flat on-resistance, a TG is commonly used as an analog switch in sample-and-hold circuits, analog multiplexers, and switched-capacitor front ends. Designers size the devices to minimize charge injection and Ron variation.
Why insert buffers between cascaded transmission gates?
A TG has no gain and adds series Ron and capacitance. Cascading N of them makes the RC delay grow roughly with N². A buffer (inverter) every one or two stages restores the signal and keeps delay linear.