In short: Pass-transistor logic (PTL) builds Boolean functions by using transistors as voltage-controlled switches that steer an input to the output, cutting transistor count and area versus static CMOS — but at the cost of a threshold-voltage drop, degraded noise margins, and slower cascades unless you add restoration.
Static CMOS is the default for a reason: it is robust, rail-to-rail, and tool-friendly. But every ASIC designer eventually meets circuits where a full complementary gate is wasteful — multiplexers, XOR trees, adders, and barrel shifters. That is exactly where pass-transistor logic earns its place. Instead of pulling the output to a rail through a transistor network, PTL lets the logic inputs themselves pass through transistors to the output node. The transistor is no longer a switch to a supply; it is a switch in the signal path.
The core idea: a transistor as a switch
An NMOS transistor conducts when its gate is high. If we tie the drain to a data signal and read the source as the output, the gate becomes a control that decides whether that data reaches the output. One NMOS is a controlled switch; two of them with complementary gate signals form a 2:1 multiplexer — the canonical PTL building block. Compare the budgets: a static-CMOS 2:1 MUX needs transmission gates plus an inverter (roughly 6–8 transistors once you include select buffering), while a pure NMOS pass network can realize the same selection with as few as 2 devices for the steering core.
A 2-input XOR in static CMOS costs about 12 transistors (including input inverters). The classic complementary pass-transistor logic (CPL) XOR/XNOR pair delivers both polarities with roughly 8–10 transistors and a single internal node, which is why CPL was popular in fast datapath arithmetic.
The threshold drop: PTL's defining weakness
Here is the catch that every interview loves. An NMOS transistor passes a strong logic 0 but a weak logic 1. When the source rises toward VDD, the gate-to-source voltage shrinks until VGS = Vt, at which point the device stops conducting. The output cannot climb past VDD − Vt. With VDD = 1.0 V and Vt ≈ 0.35 V (plus body effect pushing it higher), a "logic 1" might only reach about 0.6 V.
That degraded high has three consequences: the next stage's PMOS may not fully turn off, causing static leakage current; the noise margin high collapses; and the signal slows. PMOS is the mirror image — it passes a strong 1 and a weak 0. Combine them and you get a transmission gate, which is the standard fix.
Rule of thumb: NMOS = strong 0 / weak 1; PMOS = strong 1 / weak 0. A transmission gate (parallel NMOS + PMOS) passes both rails fully, at the cost of two devices and a complementary control signal.
Restoring the levels
Because a weak 1 leaks and loses margin, practical PTL inserts level restoration. The common trick, used in the LEAP and CPL families, is a small PMOS "keeper" (feedback pull-up) on the output: once a CMOS inverter sees the rising node cross its switching threshold, the keeper PMOS yanks the node fully to VDD, eliminating the drop and killing the leakage path. This is the heart of Double Pass-transistor Logic (DPL) and the swing-restored structures you will find in cell libraries.
PTL versus static CMOS — the trade-off table
| Aspect | Static CMOS | Pass-transistor logic |
|---|---|---|
| Transistors (2:1 MUX core) | ~6–8 | ~2–4 |
| Output swing | Full rail-to-rail | Degraded (NMOS) unless restored |
| Static leakage | Very low | Risk from weak-1 feeding PMOS |
| Input load | Drives transistor gates | Drives source/drain diffusion |
| Best fit | Random logic, control | MUX, XOR, adders, shifters |
| Tool/library support | Universal, mature | Limited; often custom cells |
A subtle but important point for timing closure: in CMOS the input drives a gate (near-pure capacitance), but in PTL the input drives a source/drain diffusion and must supply the switching current. That changes how you model drive strength, and it is one reason pass-transistor networks rarely cascade more than 3–4 deep before a buffer is required — series resistance of stacked switches degrades the RC path quadratically with depth.
Where PTL shows up in real silicon and tools
You will find pass-transistor styles inside arithmetic blocks — carry chains, 4:2 compressors in multipliers, and crossbar/barrel-shifter datapaths — where the regularity pays off. In a standard-cell flow with Synopsys Design Compiler or Cadence Genus, the synthesizer will not spontaneously emit PTL; it maps to the complementary cells in the library. PTL therefore appears either as hand-crafted custom cells characterized with Siemens Eldo / Cadence Spectre and Liberty-abstracted, or in full-custom datapath tiles laid out in Cadence Virtuoso. If you are designing those cells, you must verify the restored high level and leakage across PVT corners, because a cell that works at TT may leak badly at the fast-NMOS/slow-PMOS corner.
The transmission gate deserves its own study because it is the clean, swing-complete cousin of a bare pass transistor — see our deep dive on the transmission gate in VLSI, and for the arithmetic payoff, our walkthrough of full-adder design in CMOS shows exactly where PTL XOR cells cut area. If you want structured, interview-focused coverage of all of this, our VLSI design courses build it up from devices to datapaths. For production chip-design services that use these datapath styles in real tape-outs, our design partner Avecas VLSI design services is a good reference point.
Ready to master datapath design and ace the transistor-level questions interviewers actually ask? Enroll in the CourseTron VLSI Physical Design track and build real adders, MUXes, and PTL cells from scratch.
Frequently asked questions
Why does NMOS pass a weak 1?
As the source node charges toward VDD, VGS falls. Conduction stops once VGS drops to Vt, so the output clamps at VDD − Vt. Body effect raises Vt further, making the degradation worse at higher output voltages.
Is a transmission gate the same as pass-transistor logic?
A transmission gate is a specific PTL element: an NMOS and PMOS in parallel with complementary gate signals. It restores full swing in both directions, so it avoids the threshold-drop problem of a single pass transistor, at the cost of a second device and a complementary control line.
When should I choose PTL over static CMOS?
Choose PTL for regular, MUX- or XOR-heavy datapaths where its lower transistor count and smaller area win — provided you add level restoration and keep cascades shallow. Keep random control logic and anything leakage-critical in robust static CMOS.
Do synthesis tools generate PTL automatically?
No. Synopsys Design Compiler and Cadence Genus map to the complementary cells characterized in the standard-cell library. PTL enters the flow as custom-characterized cells or hand-designed full-custom datapath tiles.