In short: You fix a hold violation by adding delay (usually buffers or delay cells) on the fast data path so data arrives after the capture clock edge — but you must pick small, low-drive cells on near-zero-slack segments and re-check setup every time, because every picosecond you add to help hold is subtracted from the setup margin on that same path.
Why hold is the dangerous one
Setup and hold are the two sides of every sequential timing check, but they behave very differently. A setup failure means the circuit is simply too slow for the target frequency — you can usually slow the clock down and ship. A hold failure is frequency-independent: the data raced through combinational logic and overwrote the flop before the clock edge that was supposed to capture the previous value reliably latched it. Slowing the clock does nothing. If a hold violation escapes to silicon, the chip is dead at any speed, which is why hold closure is treated as a hard sign-off gate in tools like Synopsys PrimeTime and Cadence Tempus.
The governing relation for a hold check is:
T_launch + T_ck2q + T_data_min ≥ T_capture + T_hold + T_skew
Rearranged, hold slack = (data arrival, minimum delay) − (data required time). When that slack goes negative, the cure is to make T_data_min larger — deliberately insert delay so the earliest-possible data transition lands safely after the active clock edge at the capture flop.
The setup/hold trade-off you cannot ignore
Here is the core engineering tension. A buffer you add to rescue hold sits on the same physical path that setup is checked on. Its delay helps hold (it pushes data later) but it hurts setup by exactly the same amount. On a path that is comfortably fast this is free money. On a path that is already tight for setup, a careless hold fix flips a hold violation into a setup violation — the classic "whack-a-mole" that wastes days of ECO churn.
Rule of thumb: a hold violation of X ps needs roughly X/d buffers, where d is the min delay one buffer adds (often 15–40 ps for a small inverter pair at 7nm). Always leave a guardband of 10–20 ps beyond the raw violation to cover OCV/on-chip variation and routing parasitics.
Because of this, hold fixing is almost always done after setup closure and clock-tree synthesis, late in the physical flow. The physical-design engineer runs an ECO (fix_eco_timing -type hold in PrimeTime, or optDesign -postRoute -hold in Cadence Innovus) that searches for cells where adding delay is safe, then legalizes and re-routes them.
Buffer selection — which cell, and where
Not all delay cells are equal. The tool (and a good engineer) weighs several factors:
- Delay cells vs. buffers. Standard-cell libraries ship dedicated
DELcells (e.g.DEL1,DEL4) tuned to add delay with minimal area and a balanced rise/fall. They are preferred over functional buffers for pure hold padding. - Low drive strength. A weak cell (
X1,X2) adds more delay per unit area and keeps the setup penalty modest. High-drive buffers are the wrong choice — they add little delay but a lot of capacitance and leakage. - Pick the path with the most setup slack. If data fans out to several endpoints, insert the delay on the branch whose setup slack can absorb it, ideally close to the capture flop so only the failing endpoint is affected.
- Watch leakage and area. On a large SoC a single hold ECO can insert tens of thousands of cells. Prefer multi-bit or low-leakage (HVT) delay cells where timing allows — HVT cells are intrinsically slower, which is exactly what you want here.
| Scenario | Good choice | Why |
|---|---|---|
| Small hold fail, tight setup | HVT DEL1 (low drive) | Max delay/area, low setup hit, low leakage |
| Large hold fail (>100 ps) | Chain of DEL4 cells | Predictable, legalizable, routable |
| Hold on a clock-gating path | Fix via CTS skew, not data buffers | Avoid corrupting clock timing |
| Hold only in fast corner | Add guardband delay | Covers FF/low-temp (fast) corner |
Corners, OCV and multi-mode sign-off
Hold is worst in the fast process corner (FF transistors, low temperature, high voltage) because that is where the data path races fastest. A fix validated only in the typical corner can still fail silicon. Modern flows sign off hold across all MMMC (multi-mode multi-corner) scenarios simultaneously, and apply AOCV/POCV (advanced/parametric on-chip variation) derates so a buffer that looks sufficient in one corner carries enough margin everywhere. This is also why you never over-pad: extra hold buffers in the fast corner become setup liabilities in the slow corner.
A worked example
Suppose FF2 reports a hold slack of −38 ps in the fast corner. Clock skew between FF1 and FF2 is +12 ps (capture clock arrives later, which actually helps hold here), library hold requirement is 20 ps, and your smallest HVT delay cell adds ~22 ps of min delay. One cell closes the raw 38 ps but leaves almost no margin. The pragmatic fix: insert two DEL1 cells (~44 ps) near FF2's D pin, giving ~6 ps of positive slack after the fix plus derate. You then confirm FF2's setup slack was, say, +180 ps — after the 44 ps penalty it is still +136 ps, so setup is safe. This "check setup after every hold ECO" discipline is the single most common thing junior engineers forget, and it is a favourite interview question.
Never fix a data-path hold problem by adding delay to the clock tree unless you fully understand the downstream skew impact — a clock change ripples to every flop it feeds and can create new hold failures elsewhere. Teams at design houses such as Avecas VLSI design services treat clock-based hold fixes as a last resort.
Where this sits in the flow
Hold-buffer insertion is one technique inside the broader discipline of hold violation fixing. It pairs with useful-skew clock-tree tuning, data-path retiming, and VT swapping. A healthy sign-off philosophy fixes hold with the cheapest lever first: lean on existing skew and cell sizing before you carpet a block with delay cells, because every buffer is area, leakage, and a new node that must be routed and re-verified.
Want to run a real Genus-to-Innovus hold ECO on an industry PDK and read the slack reports yourself? The hands-on physical-design track at CourseTron walks you through setup/hold closure on a live block. For instructor-led VLSI training see ChipXpert.
Frequently asked questions
Can I fix hold by just slowing the clock?
No. Hold is a short-path check between two edges of the same clock event and is independent of clock period. Slowing the clock only affects setup. Hold must be fixed with added data-path delay, skew adjustment, or retiming.
Why not use a big high-drive buffer to add delay?
High-drive buffers add very little intrinsic delay but a lot of input capacitance and leakage. For padding you want the opposite — small, low-drive or HVT delay cells that add maximum delay per unit area with minimal setup and power cost.
In which corner is hold worst?
The fast corner: FF process, low temperature, high voltage. That is where the data path propagates fastest and is most likely to beat the capture edge. Always sign off hold across all corners with OCV derates applied.
How many buffers will a hold fix need?
Roughly (violation + guardband) divided by the min delay of one cell. A 38 ps violation with a 22 ps/cell delay and a 10 ps guardband needs two cells. Over-padding wastes area and can cause setup failures in the slow corner.