VLSI

Useful Skew in VLSI: Time Borrowing Explained

By CourseTron Team · 7 min read · Updated Oct 2026

Table of Contents

In short: Useful skew in VLSI is the deliberate adjustment of individual clock-arrival times so that slack is shifted from a critical timing path to an adjacent one, effectively letting a slow stage "borrow" time from a fast neighbour. Instead of insisting every flop clock arrives simultaneously (zero skew), the tool schedules a small positive or negative skew per register to close setup or hold violations and lift maximum frequency.

What Is Useful Skew in VLSI?

Useful skew in VLSI refers to the intentional, engineered difference in clock-arrival times between a launch flip-flop and its capture flip-flop, used to improve timing closure rather than being treated as an error. Classical clock-tree synthesis chases zero skew, where every endpoint receives the clock edge at the same instant. Useful skew abandons that ideal on purpose: if a data path between two flops is too slow for setup, delaying the capture clock by a few picoseconds gives that path extra time, while advancing the launch clock of a later path keeps the downstream stage healthy.

The key insight is that skew is not globally free money — it is a redistribution. Pushing the capture edge later relaxes the setup check on the path arriving at that flop, but it simultaneously tightens the setup check on the path leaving that same flop (and loosens hold on the incoming path). Useful skew works because a design is a graph of registers, and slack can be moved along that graph toward wherever it is needed most.

How Does Useful Skew Work? The Setup and Hold Equations

For a single register-to-register path, the setup constraint with skew is:

T_launch + T_cq + T_logic + T_setup ≤ T_period + T_capture

Here T_launch and T_capture are the clock-arrival times at the launch and capture flops. The skew for this path is T_capture − T_launch. A positive skew (capture arrives later than launch) adds directly to the available time, relaxing setup. The hold constraint moves the opposite way:

T_launch + T_cq + T_logic(min) ≥ T_capture + T_hold

Same path, same delays: moving the capture edge later by the skew relaxes the setup constraint.

So positive skew that helps setup makes hold harder, and vice versa. Useful-skew optimisation is therefore a constrained problem: find a per-register clock-latency assignment that maximises the worst setup slack without driving any hold slack negative, across thousands of overlapping paths at once.

Key fact: Useful skew cannot raise the frequency beyond the limit set by the slowest loop in the design. Around any register feedback loop the skews algebraically cancel, so the average cycle time of the loop is the true floor. Skew only rebalances slack between registers — it cannot create it inside a reconvergent cycle.

Delaying the clock of FF B lends time to the slow path from FF A and takes it from the fast path to FF C.

Why Use Useful Skew? Benefits in Physical Design

Higher clock frequency: by spreading slack across pipeline stages, the achievable period drops toward the true loop limit instead of being pinned by one unbalanced stage.
Setup and hold closure without logic rework: small latency tweaks fix violations that would otherwise demand resynthesis, buffer insertion, or restructuring.
Power and area savings: if skew relaxes a critical path, the tool can down-size cells or avoid high-drive VT swaps on that path.
Hold-fix leverage: advancing a capture clock can remove hold violations that would otherwise need dozens of delay buffers.

Types and Variants of Clock Skew

Positive vs negative skew

Positive skew (capture later than launch) aids setup and hurts hold; negative skew (capture earlier) aids hold and hurts setup. Useful skew deliberately chooses the sign per path.

Animation: the capture clock edge of FF B is delayed by +Δ until it lands after the slow data arrives.

Local vs global skew

Local skew is the difference between two directly communicating flops — the only kind that affects timing checks. Global skew is the spread between the earliest and latest endpoints in the whole tree and matters mainly for clock-domain and I/O budgeting.

Useful skew vs clock latency / time borrowing

Useful skew is applied to edge-triggered flops through clock-tree latency. Time borrowing is a related but distinct effect specific to level-sensitive latches, where slack passes through a transparent latch window automatically. Both move slack between stages, but skew is scheduled by the tool while latch borrowing is a property of the latch.

How to Apply and Fix Timing with Useful Skew

Enable concurrent clock and data (CCD) optimisation so the tool co-optimises clock latency with datapath sizing.
Set per-path or per-skew-group limits — bound the maximum insertion-delay spread so the clock tree stays buildable and OCV-robust.
Protect hold explicitly — give hold a positive margin target so setup-driven skew does not create new hold failures.
Re-run CTS and routing because the skew schedule is only real once the clock tree is physically built with those latencies.
Sign off with OCV/AOCV/POCV — on-chip variation erodes skew benefit, so always verify that the borrowed margin survives derating.

How EDA Tools Handle Useful Skew

Modern implementation flows fold useful skew into clock-tree synthesis and post-CTS optimisation. Cadence Innovus performs it through CCOpt (Concurrent Clock Optimisation), which builds a skewed clock tree and sizes data logic together rather than building a balanced tree first. Synopsys ICC2 and Fusion Compiler use concurrent clock and data (CCD) optimisation with the same philosophy. In both, the tool solves a linear-programming-style slack-redistribution problem across the register graph, honours skew-group and insertion-delay constraints, and inserts or resizes clock buffers to realise the target latencies. Engineers steer the result with skew limits, hold margins, and useful-skew enable switches rather than hand-assigning latencies.

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Useful Skew Interview FAQ

Does useful skew increase total clock power?

Usually a little, because realising non-zero latencies needs extra or resized clock buffers. But the net effect is often favourable: the relaxed critical paths allow smaller, lower-leakage data cells, and the tool may save more datapath power than the clock tree costs.

Can useful skew raise frequency without limit?

No. Skews cancel around any register loop, so the slowest feedback loop sets a hard floor on the cycle time. Useful skew only rebalances slack between stages; it cannot beat the average delay around a reconvergent cycle.

Why is useful skew risky under on-chip variation?

Intentional skew relies on a precise difference between two clock-arrival times. OCV, jitter, and aging make those arrivals uncertain, so a large skew that looked safe at nominal can collapse at signoff. That is why tools cap insertion-delay spread and you sign off with AOCV/POCV derating.

What is the difference between useful skew and clock jitter?

Useful skew is a deterministic, intended, static difference in clock arrival engineered by the tool. Jitter is random cycle-to-cycle variation in the clock edge that always consumes margin. One is a design knob; the other is noise you budget against.

Related reading: continue with the Antenna Effect in VLSI, keep the VLSI Glossary handy, and drill the full set of Physical Design Interview Questions.