The most-asked Physical Design interview questions with clear, correct answers from industry engineers — timing, CTS, IR drop, EM, crosstalk, power gating and more.
Master Physical DesignPhysical Design interviews at Qualcomm, Intel, NVIDIA, and AMD test the full RTL-to-GDSII flow, timing, and signoff. Below are the core questions you must know cold, each with a concise expert answer.
Setup time is the minimum time data must be stable before the active clock edge; hold time is the minimum time it must stay stable after. Setup violations are fixed by reducing data-path delay; hold violations by adding data-path delay.
CTS distributes the clock to all sequential elements while minimizing skew and insertion delay, managing power, and meeting OCV/SI requirements. Structures include H-tree, mesh, and buffered trees.
Skew is the clock arrival-time difference between launch and capture flops. Positive skew helps setup but hurts hold; negative skew helps hold but hurts setup. Useful skew balances timing intentionally.
IR drop is the supply-voltage drop across the power network (static + dynamic). Excess IR drop slows cells and risks failure. Controlled with a strong power grid, decaps, and proper strap sizing.
Global placement finds approximate cell locations minimizing wirelength/congestion; detailed placement legalizes cells onto rows and optimizes locally for timing and routability.
Congestion arises when routing demand exceeds track supply (high density, poor floorplan). Fixes: lower utilization, placement blockages, floorplan/macro adjustments, congestion-driven placement, and logic restructuring.
Long metal connected to a gate accumulates charge during fab, damaging gate oxide. Fixes: antenna diodes, layer hopping to break long nets, and antenna-aware routing.
On-Chip Variation models cell-to-cell behavior differences from PVT variation. STA applies derating (AOCV/POCV/SOCV) to launch/capture paths for robust timing closure.
Max (setup) analysis uses worst-case slow delays to verify data arrives before the next edge. Min (hold) analysis uses best-case fast delays to verify data does not change too soon. Both must pass across all corners.
A multicycle path is told to STA to allow N clock cycles instead of one (e.g., slow datapaths). A false path is a topological path never exercised functionally (e.g., across async domains) and is excluded from timing.
Floorplanning defines die/core size, macro placement, I/O and pad locations, power planning, and blockages. A good floorplan is the foundation for placement, routing, and timing success.
EM is the gradual displacement of metal atoms under high current density, causing opens/shorts over time. Mitigated by widening wires, adding vias, limiting current density, and EM-aware routing.
Crosstalk is unwanted coupling between adjacent nets causing delay (delta delay) or glitches (noise). Reduced by spacing, shielding, layer assignment, buffer insertion, and net ordering.
Power gating shuts off supply to idle blocks via header/footer switches to save leakage. Retention flops preserve critical state during power-down using an always-on backup, enabling fast wake-up.
CTS builds the clock distribution network. HFNS (High Fanout Net Synthesis) buffers high-fanout non-clock nets like resets and enables to meet transition/timing without skew balancing.
Timing closure is iterating placement, CTS, and routing until all paths meet setup/hold across corners. Fixes: VT-swap cells, upsize/downsize, restructure logic, useful skew, buffer insertion, and ECO routing.
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