In short: A hold violation means a flip-flop's data path is too fast, so you fix it by adding delay (buffers, delay cells, or longer routing) on the short path — and because it is a race against a fixed capture edge, hold can fail at any clock frequency, even 1 Hz.
What a hold violation actually is
Every flip-flop needs its D input to stay stable for a short window after the active clock edge. That window is the hold time (thold). A hold violation occurs when new data arrives at the capture register's D pin too soon after the same edge that is supposed to latch the old data — the new value races through the combinational logic and corrupts the bit before the flop has finished sampling.
Formally, hold is satisfied when:
Tlaunch + Tclk→q + Tdatapath ≥ Tcapture + thold
Notice what is missing: the clock period. Setup checks compare against the next edge (period minus skew), but hold checks the launch and capture edges that are the same edge. That single fact is why hold is frequency-independent.
Key fact: Slowing the clock down never fixes hold. If a design has a hold violation at 2 GHz, it has the exact same violation at 10 MHz, because both the launch and capture flops see the same rising edge.
Why hold fails: the three usual culprits
- Clock skew. If the capture clock arrives later than the launch clock (positive skew toward capture), the capture window shifts forward and eats into the hold margin. Skew is the number-one cause in real post-CTS designs.
- Short data paths. Two back-to-back flops with only a wire or a single inverter between them. Tdatapath is almost zero, so any skew breaks hold.
- Fast corners and OCV. Hold is checked at the fast process corner (SS is for setup, FF/fast-fast is for hold) where cells switch quickest and Tclk→q + Tdatapath is smallest. On-chip variation (OCV) derating makes the data path faster and the clock path slower, tightening hold further.
Buffer insertion — the primary fix
Since hold needs more data-path delay, the direct remedy is to insert delay on the violating path. During the hold-fixing step of place-and-route (route_opt in Synopsys ICC2 / optDesign -hold in Cadence Innovus), the tool automatically pads short paths.
Example: a path reports a hold slack of −45 ps. A standard delay buffer (say a BUFD2 with ~30 ps intrinsic delay) is not quite enough, so the tool inserts two of them, or one BUFD4, to add ~55 ps. New slack becomes +10 ps — just positive, with margin left for sign-off. The tool chooses the smallest insertion that clears the violation to avoid wasting area and leakage.
Key fact: Prefer dedicated delay cells (DEL* cells in the library) over chains of ordinary buffers. A delay cell gives a large, well-characterized delay in one footprint, so a −120 ps violation might take one DEL cell instead of four buffers — saving area, routing and leakage.
Delay cells vs. buffers vs. rerouting
| Technique | Delay added | When to use | Cost |
|---|---|---|---|
| Standard buffer (BUF) | ~15–60 ps each | Small violations, plentiful cells | Low; chains waste area |
| Delay cell (DEL) | ~80–300 ps each | Large, concentrated violations | Larger footprint, one hop |
| Detour routing / layer swap | tens of ps | Minor fixes with no free sites | Routing congestion |
| Downsize driver | small negative | Fine-tuning after CTS | May re-break setup |
Where hold fixing happens in the flow
Hold is addressed after clock tree synthesis (CTS), because real clock skew is unknown until the clock tree is built. The standard sequence is: synthesis → placement → CTS → post-CTS hold fix → routing → post-route hold fix (final). Static timing analysis in Synopsys PrimeTime signs off both setup and hold across every corner and mode — which is where multi-mode multi-corner (MMMC) analysis becomes essential, since a path can be hold-safe at the typical corner but fail at fast-fast, low-temperature.
A worked sign-off example
Suppose PrimeTime reports: launch clock 0 ps, Tclk→q = 40 ps, Tdatapath = 25 ps (one inverter), capture clock skew = +50 ps, thold = 30 ps. Data arrives at 0 + 40 + 25 = 65 ps; the requirement is 50 + 30 = 80 ps. Slack = 65 − 80 = −15 ps: a hold violation. Inserting one BUFD2 (~30 ps) pushes arrival to 95 ps → slack +15 ps. Critically, you must re-check setup on that same path afterward, because the 30 ps you just added also subtracts from setup margin. This setup-vs-hold tension is why hold cells should be inserted at the capture end and kept minimal. Teams at Avecas VLSI design services treat this balance as a core sign-off discipline.
Want to run these fixes yourself in Innovus and PrimeTime on real PDKs? The CourseTron Physical Design course walks you through CTS, hold closure and MMMC sign-off on industry tools — hands-on, not slideware.
Common mistakes engineers make
- Trying to fix hold by lowering frequency — it does nothing.
- Fixing hold before CTS, when skew is still ideal and meaningless.
- Over-padding: adding 200 ps of buffers when 20 ps was needed, breaking setup on the return path.
- Ignoring the fast corner — signing off hold only at the typical corner.
For a deeper look at the setup side of the same race, see our companion article on fixing setup violations.
FAQ
Why can't I fix a hold violation by slowing the clock?
Because hold compares the launch and capture events on the same clock edge. The clock period only appears in the setup equation (next edge), not the hold equation. Lowering frequency widens the period but leaves the same-edge race untouched.
At what process corner is hold checked?
At the fast corner (fast-fast, low temperature, high voltage), where cells switch quickest and the data path delay is smallest — the worst case for a short-path race.
Does fixing hold hurt setup timing?
Yes. Every delay element you add to satisfy hold also eats into setup slack on that path. The tool and the engineer must keep insertion minimal and verify setup still passes afterward.
Buffer or delay cell — which should I use?
Use delay cells for large or concentrated violations (more delay per footprint, less leakage), and standard buffers for small fixes or where delay cells aren't placed nearby. Most P&R tools pick automatically, but a good floorplan with delay cells available improves closure.