In short: A topological qubit stores information in the global braiding pattern of quasiparticles called anyons, so local noise cannot easily corrupt it, but after two decades of effort no one has yet shown a topological qubit that beats ordinary error-corrected qubits.
The problem topology is trying to solve
Today's superconducting and trapped-ion qubits are fragile. A transmon loses its state in roughly 100 microseconds, and two-qubit gate errors sit around 0.1 to 1 percent. To run something like Shor's algorithm on a 2048-bit key you would need logical error rates near 10-12, so the standard answer is software error correction: the surface code, with a threshold near 1 percent and an overhead of hundreds to thousands of physical qubits per logical qubit. We covered that scaling story in our quantum computing chip primer.
Topological quantum computing asks a different question. Instead of fighting errors with redundancy after the fact, can the hardware be built so that the relevant errors are physically suppressed? The idea comes from Alexei Kitaev's 2003 proposal of fault-tolerant computation by anyons.
Anyons and braiding in plain terms
In three dimensions, swapping two identical particles gives either a plus sign (bosons) or a minus sign (fermions). Confine particles to a two-dimensional plane and the exchange path can wind around other particles, which opens a third option: anyons, whose exchange multiplies the wavefunction by an arbitrary phase. Even more interesting are non-Abelian anyons. When several are present, the system has a degenerate ground space, and exchanging two of them applies a unitary matrix that rotates the state inside that space.
Key fact: the result of a braid depends only on the topology of the worldlines (how they wind), not on the exact path, the speed, or small wobbles in it.
That is the computing primitive. Pairs of non-Abelian anyons encode a qubit, and moving them around each other is a quantum gate.
Why that gives intrinsic error protection
The protection has two layers. First, the qubit's information is stored non-locally: it is spread across two or more anyons that may sit micrometres apart, so a local disturbance such as a stray charge or a flipped spin touching one anyon cannot read or change the shared state. Second, there is an energy gap. Creating a stray excitation costs energy, so at temperatures far below the gap thermal errors are exponentially rare, roughly scaling as exp(-gap / kBT).
A useful comparison is the surface code: it builds the same non-local encoding in software, using many noisy qubits and repeated syndrome measurement. A topological qubit would get part of that for free from physics, which in principle cuts both the overhead and the control burden.
| Property | Transmon + surface code | Topological (Majorana-based) |
|---|---|---|
| Protection source | Software redundancy | Physics: gap plus non-local encoding |
| Typical operating point | ~10 to 20 mK | ~10 to 50 mK, gap of order 0.1 meV |
| Native gates | Full universal set (noisy) | Clifford via braiding or parity measurement; T gates need extra help |
| Maturity | Hundreds of qubits, logical memories shown | Single devices, qubit properties still disputed |
Where the anyons come from: Majorana zero modes
The most pursued route is the Majorana zero mode (MZM). In Kitaev's toy model, a 1D chain of spinless fermions with p-wave superconducting pairing has an unpaired Majorana mode at each end. Two of them together make one ordinary fermion level, which is either empty or filled, giving a parity bit. Real devices imitate this with a semiconductor nanowire (indium arsenide or indium antimonide) with strong spin-orbit coupling, covered by a superconductor such as aluminium, in a magnetic field. Microsoft's more recent platform uses InAs/Al heterostructures patterned into H-shaped "tetron" islands.
Majoranas in a wire network are Ising-type anyons. Braiding them gives only Clifford gates, so universality still needs non-topological "magic state" distillation. Fibonacci anyons, which would be universal by braiding alone, are expected in more exotic fractional quantum Hall states and have not been demonstrated as usable qubits.
Key fact: in wire networks, braiding is often replaced by measurement-based schemes: you read out joint parity of pairs of Majoranas with an interferometer, which implements the same Clifford operations without physically moving anything.
See it move: braiding on a T-junction
Wire networks cannot braid in 1D directly, so a T-junction is used. The animation below shows the standard three-step exchange, where one Majorana is parked in the side branch while another passes through.
Where the experiments actually stand
- 2012 onward: Delft reported zero-bias conductance peaks in InSb wires, the expected Majorana signature. Disorder and Andreev bound states can mimic it.
- 2018 retraction: A high-profile Nature paper claiming quantized Majorana conductance was retracted in 2021, a reminder of how easy it is to fool yourself with a single signature.
- 2023: Google (superconducting processor) and Quantinuum (trapped ions) simulated non-Abelian anyon braiding on conventional qubits. This verifies the maths and gate-level behaviour, not a natural protected qubit.
- February 2025: Microsoft announced a "topological core" chip, Majorana 1, and published interferometric single-shot parity measurements. Independent physicists noted that the data show a measurable parity signal but do not by themselves prove topological Majoranas, and the paper's editors said the same.
The open questions are concrete: demonstrating a genuine topological gap larger than disorder, measuring parity lifetimes far longer than microseconds-to-milliseconds, showing parity-measurement error below a few percent, and ultimately a logical qubit whose error rate drops as you scale. Until a head-to-head benchmark against a surface-code logical qubit exists, topological qubits remain a high-risk, high-reward bet.
Key fact: "topological" does not mean "error-free". Quasiparticle poisoning, finite temperature and imperfect gates still introduce errors, just from different mechanisms.
The chip-design angle
Even a perfect topological qubit needs classical silicon around it. Cryogenic control (cryo-CMOS) at 4 K to drive gates and read parity must be designed with accurate cold device models in tools such as Cadence Virtuoso and Spectre or Synopsys custom design flows, and materials teams use atomistic simulators like Synopsys QuantumATK for heterostructure modelling. If you want to build the classical half of a quantum computer, start with strong analog and mixed-signal fundamentals; the training team at ChipXpert covers that practical design flow, and our error correction basics article explains the surface-code alternative in more depth.
Want to go from quantum concepts to real chip design? Explore the hands-on VLSI and quantum hardware tracks on the CourseTron courses page.
FAQ
Are anyons real particles?
They are quasiparticles: collective excitations of many electrons in a 2D material or a superconductor-semiconductor hybrid. They are not elementary particles, but they obey well-defined exchange statistics.
Does a topological qubit need no error correction?
No. It lowers the physical error rate substantially, but practical algorithms still need some error correction, and magic state distillation for Ising-type anyons.
Has Microsoft built a working topological qubit?
Microsoft has reported devices and parity measurements consistent with its design, but the community has not accepted that a protected topological qubit has been demonstrated.
Why is it so hard to confirm a Majorana?
Conductance peaks and similar signatures can come from ordinary disorder-induced states. A convincing proof needs several independent tests, such as non-local correlations and coherent parity dynamics.