In short: A quantum processor is a stack of superconducting circuits (transmon qubits, coupler, drive/flux lines and readout resonators) fabricated on a silicon or sapphire die, flip-chip packaged and cooled to about 10 mK, and it stops scaling when per-qubit wiring, heat load and junction-fabrication yield outgrow the fridge and the foundry.
What is actually on the die
The most mature quantum chips today, from IBM, Google and Rigetti, use superconducting transmon qubits. A transmon is an anharmonic LC oscillator: a large capacitor in parallel with a Josephson junction, a thin Al/AlOx/Al sandwich that acts as a nonlinear, lossless inductor. Because the junction makes the energy ladder uneven, the 0→1 transition (typically 4–6 GHz) can be addressed without accidentally driving 1→2.
Everything else on the die is passive microwave plumbing: niobium or aluminium coplanar waveguides, capacitor pads, couplers and resonators patterned on high-resistivity silicon or sapphire. Superconducting films have essentially zero resistance below their critical temperature (aluminium about 1.2 K, niobium about 9 K), which is why the circuit can hold a quantum state for 100 µs or more, the coherence time called T1.
Key fact: A qubit is not a transistor. It is an analog microwave resonator whose frequency, around 5 GHz, is set by the junction's critical current, so fabrication precision directly sets computational quality.
Qubit layout and coupling
Qubits are placed on a sparse 2D graph, because each added neighbour adds crosstalk and frequency collisions. Google's Sycamore-style chips use a square grid; IBM uses a heavy-hex lattice where each qubit has two or three neighbours. Neighbours talk through a fixed capacitor or a tunable coupler, a SQUID-based element whose effective coupling is switched from nearly zero to tens of MHz by a flux pulse.
Frequency planning is a layout problem much like clock-skew or crosstalk closure in digital design: adjacent qubits must be detuned by a few hundred MHz, and next-nearest neighbours must avoid the 1→2 transition and spectator collisions. A two-qubit gate takes about 30–100 ns, so a 100 µs T1 gives roughly 1,000 gates of budget before decay dominates.
Control lines and readout resonators
Every qubit needs at least two inputs. The XY line delivers shaped microwave pulses (typically 20–50 ns Gaussian or DRAG envelopes) that rotate the state. The Z line carries a flux bias that tunes frequency in tunable-transmon designs. Couplers need Z lines too, so a naive chip carries about 2–3 control lines per qubit.
Readout is dispersive. Each qubit is capacitively coupled to a λ/4 coplanar resonator near 6–7 GHz. The resonator frequency shifts by a few MHz depending on whether the qubit is in |0⟩ or |1⟩, so a probe tone reflecting off it comes back with a different phase. Many resonators, each at a distinct frequency, share one feedline (frequency-division multiplexing), so one output line reads 5–10 qubits. The faint signal, on the order of a few photons, is first boosted by a Josephson parametric amplifier (JPA) or travelling-wave parametric amplifier (TWPA), then by a cryogenic HEMT amplifier at 4 K.
Cryogenic packaging
The die sits in a gold-plated copper or aluminium box on the mixing-chamber plate of a dilution refrigerator at about 10–20 mK. Thermal energy at that temperature (kT/h is roughly 0.2 GHz) is far below the 5 GHz qubit quantum, so the qubit rests in its ground state. At room temperature, kT/h is about 6 THz and the state would be a random mess.
The package is a microwave-and-magnetics engineering job. It needs a superconducting or mu-metal shield against stray flux, infrared-blocking filters and Eccosorb absorbers against quasiparticle-generating photons, and a box whose lowest cavity mode sits far above 7 GHz, otherwise the box itself becomes a lossy resonator. Package modes and wirebond inductance are simulated in Ansys HFSS, Cadence AWR Microwave Office or Sonnet. Open-source Qiskit Metal and KLayout generate the layout, while foundry-style rule decks (DRC) can be written in Siemens Calibre or Synopsys IC Validator.
Larger chips use flip-chip bonding: a qubit die and a wiring/readout die are joined face to face by indium bumps, with through-silicon vias (TSVs) bringing signals to the back. This is the same 3D integration logic as HBM memory, just superconducting.
Why wiring limits scaling
Today's systems, such as 100–1,000 qubit chips, use about 2–3 coaxial lines per qubit. Scale that to one million qubits and you need millions of cables entering a fridge that can remove only microwatts at 20 mK. Each attenuator also dissipates the drive power it absorbs.
| Approach | What it does | Trade-off |
|---|---|---|
| Multiplexed readout | 5–10 resonators per feedline | Needs frequency crowding control |
| Flex cables / ribbon lines | Dense stripline wiring | Crosstalk, thermal load |
| Cryo-CMOS controller | Pulse generation at 4 K | Power under ~100 mW per stage |
| SFQ logic | Superconducting digital control | Immature tooling |
Key fact: The question is not how many qubits fit on a die but how many control lines fit through the fridge. A 4 K cryo-CMOS controller with about 1 W of cooling power at that stage can afford only a few milliwatts per qubit.
Why fabrication yield limits scaling
Transmon frequency scales as √(8·EJ·EC) minus EC, and EJ follows the junction's normal-state resistance by the Ambegaokar-Baratoff relation. Shadow-evaporated junctions of about 100 nm width typically vary 2–5% in resistance, which shifts qubit frequency by 1–2.5%, or 50–120 MHz at 5 GHz. That is large compared with the few-hundred-MHz detuning budget, so collisions are inevitable on large chips. Foundries use laser annealing of junctions to trim resistance to within 0.2–0.5%.
The second yield killer is two-level-system (TLS) defects in amorphous oxides at metal-substrate and substrate-air interfaces. A TLS near a qubit's frequency steals energy and creates a bad qubit with T1 of 20 µs instead of 200 µs. Because defects are random, yield is multiplicative: if each qubit has a 99% chance of being usable, 1,000 qubits contain about 10 bad ones, and a processor with all 1,000 working has a probability of 0.991000, about 0.004%. Designers therefore route around dead qubits or accept binned parts, exactly like core-binning in CPUs.
Two-qubit gate fidelity matters more than count. At 99.9% per gate, a 1,000-gate circuit succeeds with probability about 37%. Error correction (surface code) needs about 1,000 physical qubits per logical qubit at 0.1% error rates, which is why both wiring and yield must improve together.
Where the field is heading
Different qubit types attack these limits differently. Trapped ions and neutral atoms have better uniformity but slower gates, while spin qubits in silicon reuse CMOS fabs but need even denser control. Topological qubits aim to make errors intrinsically rare; see our guide to topological quantum computing. For the error-correction side of the scaling story, read surface code error correction. If you want to design microwave and mixed-signal blocks for cryogenic control, the training team at ChipXpert runs VLSI programmes that cover the same analog and RF flows.
Want to go from device physics to chip design? Explore the hands-on semiconductor and VLSI tracks in the CourseTron course catalogue.
Frequently asked questions
Why do quantum chips need to be so cold?
Thermal noise at room temperature is thousands of times larger than the 5 GHz qubit energy, and aluminium only superconducts below about 1.2 K. At about 10 mK the thermal population is negligible and coherence lasts for hundreds of microseconds.
What is a Josephson junction?
It is two superconductors separated by an insulating oxide barrier a nanometre or two thick. It behaves as a nonlinear inductor with almost no loss, which makes the qubit's energy levels unevenly spaced so that only the 0 and 1 states are used.
Why not just add more wires?
Each coax line carries heat into stages that can remove only about 20 µW at 20 mK. Beyond a few thousand lines the fridge cannot cool, so designers use multiplexing, cryo-CMOS and flex wiring.
How is yield different from classical chips?
Classical chips tolerate parameter spread because logic is digital. A qubit's frequency is analog, so a 2% junction spread can cause collisions with neighbours and defects in the oxide can cut coherence by 10x.