In short: Useful quantum computers are blocked by fragile qubits, so noise, short coherence, dense control wiring, millikelvin cooling and drifting calibration all push you toward error correction that costs hundreds to thousands of physical qubits for every reliable logical one.
Headlines about qubit counts hide the real story. Building 1,000 qubits is an engineering feat; building 1,000 qubits that stay correct long enough to run a billion operations is a different problem entirely. This article walks through the six barriers that interviewers and architects actually discuss. If you want the upside first, read applications of quantum computing; here we focus on what stands in the way.
1. Noise: every gate is slightly wrong
A classical CMOS gate has an error rate below 10-15 per operation, so we never think about it. A superconducting transmon two-qubit gate today lands around 0.1 to 0.5 percent error, and single-qubit gates around 0.01 to 0.05 percent. Errors come from control pulse imperfection, crosstalk between neighbouring qubits, leakage out of the two-level subspace, and readout mistakes (readout is often the worst, at 0.5 to 2 percent).
Because errors compound, a circuit of 1,000 two-qubit gates at 0.3 percent error succeeds with probability roughly (0.997)1000, about 5 percent. This is why current NISQ (noisy intermediate-scale quantum) devices are limited to shallow circuits.
Key fact: Algorithms such as Shor's factoring need around 109 to 1012 reliable operations, while raw hardware manages perhaps 102 to 103. That gap of nine orders of magnitude is the core challenge.
2. Short coherence: the clock is ticking
A qubit holds a superposition only for a limited time. T1 is the energy-relaxation time (the |1⟩ state decays to |0⟩); T2 is the dephasing time, the lifetime of the phase relationship. Typical transmons show T1 of 100 to 300 microseconds today, up from about 1 microsecond in the early 2000s. Trapped-ion and neutral-atom qubits reach T2 of seconds or longer, but their gates are far slower (microseconds to hundreds of microseconds).
What matters is the ratio: how many gates fit inside the coherence window. A transmon with 50 ns single-qubit gates and 200 microsecond T1 gets thousands of gates; with 300 ns two-qubit gates and real-world T2 closer to 100 microseconds, you get only a few hundred entangling layers. Ions trade the other way: long memory, slow clock.
3. Control wiring: the "wiring bottleneck"
Each superconducting qubit needs a microwave drive line, often a flux-bias line, and a readout resonator that multiplexes onto a shared feedline. Prototype fridges use roughly 2 to 4 coaxial cables per qubit. A 1,000-qubit machine would need thousands of cables passing from room temperature to the cold plate, each leaking heat and consuming space. Scale to a million qubits and coax simply cannot fit.
Solutions under development include flexible cryogenic ribbon cables, 3D-integrated chips with through-silicon vias, and moving control electronics into the fridge as cryo-CMOS. Intel's Horse Ridge and similar academic ASICs generate qubit pulses at 4 K. Designing them needs transistor models validated at cryogenic temperatures, where threshold voltage rises and mobility changes, so analog teams extend simulators such as Cadence Spectre and Synopsys HSPICE with custom cryo corners. This is where VLSI engineers become directly relevant; our ChipXpert VLSI training covers the analog and mixed-signal skills involved.
4. Cryogenics: colder than deep space
Superconducting qubits work at about 10 to 20 millikelvin, achieved with a dilution refrigerator. The reason: transmon transition frequencies sit near 5 GHz, equal to a temperature of about 240 mK, so thermal photons must be suppressed far below that. Cooling power is tiny; a typical mixing chamber provides only about 10 to 20 microwatts at 20 mK, yet a compute stage dissipating even milliwatts is unacceptable there.
The fridge is a staged stack, each plate absorbing heat so the next stays cold. Power budgets shrink drastically as you go down, which is why control electronics at 4 K must stay within a few watts and anything at the mixing chamber within microwatts.
5. Calibration drift: the machine never stays tuned
A qubit frequency, gate amplitude and readout threshold are all tuned values. Two-level-system defects in the oxide fluctuate, cosmic rays hit the substrate, and fridge temperatures wander, so T1 on a single transmon can swing by a factor of two over hours. Operators run automated calibration graphs (Rabi, Ramsey, randomized benchmarking) that can take many minutes for a large chip and must repeat constantly. Fleet-wide, the calibration data is itself a big-data problem. Photonic and ion platforms drift too, via laser frequency and beam pointing.
Key fact: Cosmic-ray and radiation events can cause correlated errors across many qubits at once, which breaks the independent-error assumption that most error-correcting codes rely on.
6. Fault tolerance: the overhead tax
The answer to noise is quantum error correction (QEC). You cannot copy a qubit (no-cloning), so you spread one logical qubit over many physical qubits and repeatedly measure parity checks (syndromes) without measuring the data. The leading scheme is the surface code, where a distance-d patch uses d² data qubits plus d²−1 measurement qubits, so 2d²−1 total. At d = 17 that is 577 physical qubits per logical qubit.
QEC only helps below the threshold, roughly 1 percent per operation for the surface code. Google's 2024 Willow chip (105 qubits) showed the logical error rate halving as distance grew from 3 to 5 to 7, the first convincing below-threshold result. Logical error then falls exponentially as d grows, but cost grows quadratically. Estimates for factoring RSA-2048 now run to under a million physical qubits running for days, still a thousandfold beyond today's chips.
Fault tolerance has more costs: non-Clifford gates like T need magic-state distillation (a large fraction of the chip), and decoding must keep pace in real time, with latency of about 1 microsecond per syndrome round. That pushes decoders into FPGAs and ASICs, an area where RTL and timing-closure skills in Synopsys Design Compiler or Cadence Genus matter.
How the barriers compare
| Barrier | Typical number | Main mitigation |
|---|---|---|
| Gate noise | 0.1 to 0.5% two-qubit error | Better materials, pulse shaping, error mitigation |
| Coherence | T1 about 100 to 300 µs (transmon) | Tantalum films, cleaner fabrication, other modalities |
| Wiring | 2 to 4 cables per qubit | Multiplexing, cryo-CMOS, 3D integration |
| Cryogenics | 10 mK, tens of µW | Bigger fridges, modular links |
| Drift | T1 varies about 2x per day | Automated recalibration, drift-aware compilers |
| QEC overhead | 100s to 1000s per logical | qLDPC codes, better thresholds |
Key fact: Newer qLDPC (low-density parity-check) codes, such as IBM's bivariate bicycle codes, promise roughly ten times fewer physical qubits than the surface code, but they need long-range connections that make the wiring problem harder.
For a hands-on view of how concepts like superposition and gates map to hardware, see our primer on qubits and quantum gates.
What this means for engineers
Quantum hardware is now a systems problem as much as a physics one: RF design, cryogenic packaging, FPGA decoders, timing, and software for calibration. Those are the exact skills semiconductor teams already have. You can start building them through the CourseTron courses catalogue.
Ready to build the digital and analog foundations behind quantum control hardware? Explore the CourseTron VLSI and electronics courses and start learning today.
FAQ
Why can't we just add more qubits to fix errors?
More noisy qubits do not help unless they are organised into an error-correcting code operating below the threshold error rate. Without that, extra qubits add more noise sources and more crosstalk.
Why do superconducting qubits need 15 millikelvin?
Their transition energy corresponds to about 240 mK at 5 GHz. Cooling far below that keeps thermal photons from randomly exciting qubits and keeps the aluminium or niobium circuits superconducting.
What is the difference between T1 and T2?
T1 is how long a qubit keeps its energy before relaxing to the ground state. T2 is how long it keeps phase coherence; T2 is at most 2 times T1 and usually shorter due to dephasing.
How many physical qubits make one logical qubit?
It depends on the code and hardware error rate. A surface code at distance 17 uses 577; better hardware or qLDPC codes could bring it to tens or low hundreds.