In short: UCIe (Universal Chiplet Interconnect Express) is an open industry standard for connecting chiplets on a single package, so dies from different vendors and process nodes can talk over a short, dense die-to-die link. It defines a layered stack — physical, die-to-die adapter, and protocol — and supports both low-cost standard packaging and high-bandwidth advanced packaging.
A ucie chiplet interconnect is a die-to-die (D2D) link built to the UCIe specification, first released in 2022 by a consortium that includes Intel, AMD, Arm, TSMC, Samsung, Google and others. Instead of fabricating one enormous monolithic system-on-chip (SoC), designers now split the system into smaller chiplets — a CPU core complex, an I/O die, an accelerator, a memory controller — and stitch them together inside one package. UCIe is the standardized "wire and handshake" that lets those chiplets communicate reliably.
The motivation is practical. As transistors approach atomic limits, building a single large die on the newest node is expensive and yields poorly. Smaller dies yield better, can mix process nodes (logic on 3 nm, analog or I/O on a mature 7 nm), and can be reused across products like building blocks. UCIe plays the role for packages that PCIe plays for boards: a published, interoperable standard so a chiplet from one supplier drops into a design from another.
UCIe borrows the layering idea from PCI Express and splits the link into three cleanly separated layers. This separation is what lets the same protocol run over very different physical media.
The top layer carries the actual traffic. UCIe natively maps PCIe and CXL (Compute Express Link) so existing software and coherency models work unchanged across the package. For custom traffic it offers a flexible Streaming protocol, letting designers tunnel any user-defined packet format over the same link.
The adapter sits between protocol and PHY. It handles link state management, parameter negotiation, optional CRC and retry for reliability, and arbitration when multiple protocols share one physical link. It packages protocol data into fixed-size flits so the PHY sees a uniform stream regardless of what rides on top.
The PHY owns the electrical interface: the data lanes, clock forwarding, a low-speed sideband channel for management and training, and the link-training state machine that aligns and calibrates the lanes at boot. It is the only layer that physically meets the neighbouring die.
Watching a single unit of data move clarifies why the layering matters. A protocol packet is framed into a flit, the adapter adds integrity information, and the PHY serializes it across the lanes to the far die, where the stack unwinds in reverse.
UCIe defines two packaging profiles because not every product needs — or can afford — the densest option. The adapter and protocol layers stay identical; only the PHY and the physical substrate change.
Because both profiles share the upper layers, a design team can validate protocol and adapter logic once and retarget the PHY for whichever package economics the product demands.
Before UCIe, every die-to-die link was proprietary — AMD's Infinity Fabric, Intel's AIB, and others — so chiplets from different vendors could not interoperate. A published standard unlocks a genuine chiplet marketplace: a hyperscaler could buy a networking chiplet from one company, an accelerator from another, and a CPU tile from a third, then integrate them in a single package with confidence that the links will train and talk. It also standardizes test, debug and compliance, lowering the engineering risk of heterogeneous integration.
Real projects and industry tool flows, with certification.
Explore CourseTron Courses →No. PCIe connects devices across a board or through a connector; UCIe connects chiplets inside a single package over a much shorter, denser link. However, UCIe can carry PCIe (and CXL) protocol traffic natively, so the two are complementary rather than competing.
That is the goal. UCIe defines the electrical interface, the adapter behaviour and a compliance framework so interoperable chiplets can be mixed. In practice, early designs still often use chiplets from a single vendor while the ecosystem and compliance programs mature.
A flit (flow-control unit) is the fixed-size data unit the die-to-die adapter uses to packetize protocol traffic for the PHY. Working in uniform flits lets the adapter add CRC and retry and keeps the physical link format independent of the protocol on top.
Choose advanced packaging when you need maximum bandwidth density and minimum energy per bit — typical of AI and HPC accelerators. For cost-sensitive products with moderate bandwidth needs, the standard package on an organic substrate is usually sufficient.
Related: PCIe protocol basics · Glossary · all courses.