In short: MII, RGMII and SGMII are the standard digital interfaces that connect an Ethernet MAC to its PHY — they differ mainly in how many data wires they use, how fast those wires clock, and whether speed is signalled in-band or by sideband negotiation.
Almost every Ethernet-capable SoC you will design or verify has a boundary where the controller logic (the MAC) stops and the analog line driver (the PHY) begins. That boundary is a Media Independent Interface. Understanding which flavour your chip exposes — and why — is a staple interview question for anyone working on networking silicon, FPGAs, or board bring-up. This article walks through MII, RGMII and SGMII with the pin counts, clock rates and negotiation mechanics you actually need.
Why a MAC-to-PHY interface exists at all
The IEEE 802.3 model deliberately splits Ethernet into a MAC sublayer (framing, CRC, CSMA/CD history, flow control) and a Physical layer (line coding, equalization, the actual copper or optical driver). Keeping them "media independent" means one MAC RTL block can talk to a 10BASE-T, 100BASE-TX or 1000BASE-T PHY without redesign — you just swap the PHY. The interface in between carries nibble or byte data plus control, and it is where clock-domain crossing, timing closure and I/O standard selection all converge in your design.
Rule of thumb: the faster the line rate, the narrower and faster the interface tends to get — the industry traded parallel buses (MII's 4 bits) for high-speed serial (SGMII's single lane) to cut pin count on gigabit designs.
Classic MII — the 100 Mbps baseline
MII, standardized in 802.3u, is a 4-bit-wide parallel interface clocked at 25 MHz for 100 Mbps (4 bits × 25 MHz = 100 Mbps) and 2.5 MHz for 10 Mbps. It uses separate transmit and receive clocks (TX_CLK, RX_CLK) sourced by the PHY, which is the key gotcha: the MAC does not generate the clock, it receives it. A full MII link needs roughly 16 signals: TXD[3:0], TX_EN, TX_ER, TX_CLK, RXD[3:0], RX_DV, RX_ER, RX_CLK, plus CRS and COL for half-duplex. On top of that sits the two-wire MDIO/MDC management bus used to read and write PHY registers.
RGMII — gigabit with half the pins
Reduced Gigabit MII (an HP/Marvell specification widely adopted on SoCs) halves the data width to 4 bits but clocks both edges — it is double data rate (DDR). For 1000 Mbps the clock runs at 125 MHz and data is sampled on rising and falling edges: 4 bits × 125 MHz × 2 = 1000 Mbps. This cuts the data pins from eight (GMII) to four and drops the total from ~24 signals to about 12. Speed drops scale the clock: 25 MHz for 100 Mbps, 2.5 MHz for 10 Mbps.
RGMII's practical headache is the clock-to-data timing relationship. The original spec expected the board to add ~1.5–2 ns of trace delay on the clock; later "RGMII-ID" (internal delay) variants let the PHY add that skew internally via a strap or register. Getting this wrong is the classic cause of a link that trains but drops packets. In static timing closure you model these as I/O constraints, and tools like Synopsys PrimeTime or the FPGA vendor's timing engine (Vivado, Quartus) check setup/hold on the DDR captures.
SGMII — one serial lane, embedded clock
Serial GMII (a Cisco specification) takes a different path: it serializes the whole gigabit stream onto a single differential SerDes lane running at 1.25 Gbps (1 Gbps payload after 8b/10b line coding adds 25% overhead). There is no parallel data bus and no forwarded source-synchronous clock — the receiver recovers the clock from the data (CDR). Physically it is just TX± and RX± pairs plus the management bus, which is why SGMII dominates on pin-constrained, high-port-count switch and SoC designs.
SGMII never changes its line rate across 10/100/1000. At 100 Mbps each byte is simply repeated 10×, and at 10 Mbps 100×, so the SerDes always runs at 1.25 Gbps — speed is conveyed in-band, not by reclocking.
Speed negotiation: in-band vs sideband
This is where candidates often stumble. MII and RGMII do not themselves negotiate speed — the PHY performs 802.3 auto-negotiation on the copper, resolves the speed, then the MAC learns the result by reading PHY status registers over MDIO (or, for RGMII, by sampling the in-band status nibbles the PHY sends during inter-frame gaps). SGMII, by contrast, carries a 16-bit configuration word in a replacement for the auto-negotiation ordered sets: the PHY tells the MAC the resolved speed and duplex directly in-band, so the MAC adapts its byte-repetition without an MDIO round trip.
Picking one: a comparison
| Feature | MII | RGMII | SGMII |
|---|---|---|---|
| Max rate | 100 Mbps | 1000 Mbps | 1000 Mbps (+2.5G variants) |
| Data width | 4-bit SDR | 4-bit DDR | 1 serial lane |
| Clock | 25 MHz, PHY-sourced | 125 MHz DDR, fwd'd | 625 MHz recovered (CDR) |
| Data signals | ~16 | ~12 | 4 (2 diff pairs) |
| Speed signalling | MDIO | In-band nibble / MDIO | In-band config word |
| I/O standard | LVCMOS | HSTL/SSTL (2.5/1.8 V) | CML SerDes |
On an FPGA, MII/RGMII map to ordinary LVCMOS/HSTL I/O banks with DDR primitives, while SGMII requires a gigabit transceiver (GTX/GTH on Xilinx, GXB on Intel). On an ASIC, SGMII pulls in a hard SerDes macro and its PLL — a verification and signoff exercise in its own right, often handled with Cadence or Siemens (Mentor) VIP that models 8b/10b, clock recovery and the auto-negotiation state machine. If you are specifying a networking block, read our companion piece on Ethernet basics for chip design and the deeper SerDes and 8b/10b line coding walkthrough before committing to a PHY interface.
For hands-on training on building and verifying these blocks, our partner ChipXpert VLSI training runs lab-driven courses that pair the theory here with real RTL and simulation exercises.
Want to design a MAC, close RGMII timing, and verify an SGMII link end to end? Join the CourseTron Protocols & Interfaces track — browse the course catalogue.
Frequently asked questions
Why does RGMII use double data rate instead of a wider bus?
GMII already carried gigabit on 8 data bits at 125 MHz single-edge, but that is 24+ pins. RGMII keeps 125 MHz, halves the data to 4 bits, and clocks both edges to recover the lost bandwidth — saving package pins and board routing at the cost of tighter clock-to-data skew requirements.
Does SGMII support 10 and 100 Mbps?
Yes. The SerDes always runs at 1.25 Gbps; at lower speeds each data byte is simply replicated (10× for 100 Mbps, 100× for 10 Mbps). The resolved speed is carried in the in-band configuration word, so the link rate on the wire never changes.
Who generates the clock in MII versus SGMII?
In MII and RGMII the PHY forwards the receive clock and the transmit clock is source-synchronous. In SGMII there is no forwarded clock at all — the receiver's CDR recovers timing from the serial transitions, which is why SGMII needs a transceiver, not a plain I/O.
Can one MAC support all three?
Many SoC MACs expose a configurable PHY interface and a mux so the same controller can drive MII, RGMII or SGMII depending on the bonded PHY and the selected I/O. The choice is usually a strap, a register, or a synthesis-time parameter.