Ethernet basics for chip design

In short: Ethernet in a chip splits into a MAC that builds and parses frames and a PHY that drives the wire; a standard media-independent interface (MII/RGMII/SGMII) bridges the two so you can mix vendors, scale from 10 Mb/s to 10 Gb/s and beyond, and verify each block independently.

Almost every SoC that talks to the outside world — a router ASIC, an automotive gateway, a smart NIC, even a microcontroller — carries an Ethernet port. For a chip designer, "Ethernet" is not one block but a stack of well-defined layers, and the cleanest way to understand it is to follow a single frame from software down to copper or fiber. This article walks that path, names the interfaces you will actually instantiate in RTL, and points out where verification and physical design usually bite.

The two halves: MAC and PHY

IEEE 802.3 draws a sharp line between the MAC (Media Access Control) and the PHY (Physical layer). The MAC is pure digital logic that lives in your synthesizable domain: it frames data, inserts the preamble and start-of-frame delimiter, computes the 32-bit CRC (frame check sequence), handles inter-frame gap, and — on half-duplex links — runs CSMA/CD backoff. The PHY is mixed-signal: it does the line coding (4B/5B, 8B/10B, 64B/66B), serialization, clock recovery, and the analog front end that actually swings volts on the medium.

Why the split matters: the MAC is media-independent. The same MAC RTL can drive a 100BASE-TX twisted-pair PHY today and a 1000BASE-KX backplane SerDes tomorrow — only the PHY and the pin-level interface change. That reuse is the entire point of the architecture.

The interface zoo: MII, RMII, GMII, RGMII, SGMII

Between MAC and PHY sits a standardized parallel or serial bus. Which one you use depends on speed and pin budget — a constant trade-off in real chip floorplans.

RGMII is the workhorse for gigabit MCUs and switches because it halves GMII's pin count by clocking data on both edges of a 125 MHz clock (double data rate). The classic RGMII headache is the ~2 ns timing delay between clock and data: you either add board trace length, enable an internal delay strap in the PHY, or let the MAC shift the clock. Get that wrong and the link trains but drops packets under traffic — a bug that only shows up in gate-level timing and on the bench, never in a naive RTL sim.

Rule of thumb: below 1 Gb/s you can afford a parallel source-synchronous interface; at 1 Gb/s and above, chips increasingly move to SGMII/USXGMII over a SerDes so the whole link rides a single differential pair and a single package ball-out.

Anatomy of an Ethernet frame

The MAC's core job is building the frame below. Every field has a reason, and interview questions love the edge cases.

The 7-byte preamble plus 1-byte start-frame delimiter give the receiver's clock-recovery loop time to lock. The 46-byte minimum payload exists so the smallest legal frame (64 bytes including header and FCS) is long enough for half-duplex collision detection to work at 10/100 — the MAC pads short payloads automatically. The FCS is a CRC-32; the receiver recomputes it and silently drops frames that fail. A VLAN tag (802.1Q) inserts four bytes after the source address and is where a lot of switch-ASIC logic concentrates.

Speed, line coding, and the PCS

As rates climb, the PHY's physical coding sublayer (PCS) does more work. 100BASE-TX uses 4B/5B coding; 1000BASE-X uses 8B/10B (25% overhead but DC-balanced and easy to recover); 10GBASE-R and faster move to 64B/66B to shrink that overhead to ~3%. Each step trades coding efficiency against clock-recovery robustness — a decision that lands squarely on the mixed-signal team but constrains the MAC's data path width and clock plan.

Watching a bit move: the animated view

What this means for your flow

In practice you integrate a vendor MAC IP (or write your own), attach a hard or soft PHY, and verify the seam. UVM testbenches with an Ethernet VIP drive and monitor the MII/GMII bus; teams use Synopsys VCS or Siemens Questa for RTL/gate simulation and Cadence Xcelium for mixed-signal co-sim when the SerDes is involved. Timing closure on RGMII and SerDes lanes runs through Synopsys PrimeTime and place-and-route tools like Cadence Innovus, where the DDR clock relationships and SerDes macro placement dominate. If you are building these flows from scratch, structured training such as ChipXpert's VLSI programs shortens the ramp considerably.

Ethernet shares many habits with other serial interconnects — framing, CRC, and clock recovery recur everywhere. If you are comparing protocols, our USB protocol basics and PCIe link-layer basics articles map the same ideas onto different wires. Browse the full set on the CourseTron courses page.

Ready to build a MAC and close timing on a real RGMII link? Join the CourseTron Protocols & Interfaces track and work through hands-on labs with industry EDA tools. Explore the course →

Frequently asked questions

Is the MAC always on-chip and the PHY always external?

Not necessarily. The MAC is virtually always inside the SoC. The PHY may be a discrete chip connected over RGMII/SGMII, or a hard macro integrated on-die — common for SerDes-based gigabit and 10G links where keeping the analog front end on-chip improves signal integrity.

Why does the smallest Ethernet frame have to be 64 bytes?

So that at 10/100 Mb/s half-duplex, a station is still transmitting when the earliest possible collision signal returns, letting CSMA/CD detect the collision. Full-duplex links do not collide, but the 64-byte minimum stayed for backward compatibility, so the MAC pads short payloads.

What is the RGMII delay problem?

RGMII clocks data on both edges of 125 MHz, so clock and data must stay aligned within a tight window. A roughly 2 ns skew is needed between them; you add it via board trace length, a PHY internal-delay strap, or MAC-side clock shifting. Mismatched settings produce intermittent packet loss.

How does the receiver detect a corrupted frame?

The transmitter appends a CRC-32 frame check sequence. The receiver recomputes the CRC over the frame and compares; any mismatch means the frame is dropped silently and left for higher layers to retransmit.