In short: MIPI D-PHY is a source-synchronous, dual-mode physical layer that carries CSI-2 camera and DSI display data as fast differential HS bursts (hundreds of Mbps to 2.5 Gbps per lane) and sips power between bursts with single-ended LP signaling, using one clock lane to strobe one or more data lanes.
Why a camera needs its own PHY
Every smartphone, automotive ADAS module, and embedded vision board faces the same problem: how do you move a 4K-at-60fps video stream from an image sensor to an SoC across a few millimeters of flex cable without burning the battery or spraying EMI across the RF front end? A naive parallel bus would need dozens of pins toggling at full rail; a plain LVDS link would waste current whenever the sensor is idle. MIPI's answer is D-PHY — the physical layer that sits beneath the CSI-2 (camera) and DSI (display) protocols. It is the invisible workhorse in virtually every mobile imaging pipeline shipped since 2010.
The defining trick of D-PHY is that each physical lane operates in two completely different electrical modes, switching between them many times per frame. Understanding that duality is the key to reading a D-PHY datasheet, debugging a bring-up, or passing a VLSI protocol interview.
HS and LP: two personalities on one wire pair
A D-PHY lane is a pair of wires (Dp/Dn). It alternates between:
- High-Speed (HS) mode — low-swing differential. The nominal common mode is 200 mV with a ~200 mV differential swing (|Vod| around 100–200 mV), terminated into 100 Ω. This is where the payload flies: a modern D-PHY v2.5 lane runs up to 4.5 Gbps symbol-coded, while classic v1.x lanes top out near 1.5–2.5 Gbps. Low swing means low dynamic power and low radiated emissions.
- Low-Power (LP) mode — single-ended, rail-to-rail (0 to 1.2 V) on each wire independently, toggling slowly (typically ≤ 10 MHz). LP is used for control: entering/leaving bursts, bus turnaround, escape commands, and the Ultra-Low-Power State (ULPS) that drops a lane to near-zero current between frames.
The same transmitter contains both a fast differential HS driver and a slow single-ended LP driver sharing the pins — the receiver watches LP line states (LP-11, LP-01, LP-00…) to know when a HS burst is about to start.
Lanes and the forwarded clock
D-PHY is source-synchronous: rather than recovering a clock from the data (as PCIe or MIPI's newer C-PHY/M-PHY do), the transmitter forwards a dedicated clock lane alongside the data lanes. The clock is a DDR half-rate signal — data is sampled on both edges, so a 1 GHz clock lane supports 2 Gbps per data lane. The receiver delays the clock by roughly a quarter unit-interval and uses it to latch every data lane.
A link has one clock lane and 1 to N data lanes (typically 1, 2, or 4). Bandwidth scales almost linearly with lane count: four lanes at 2.5 Gbps give 10 Gbps of raw HS throughput, comfortably feeding a 48 MP sensor burst. Because all data lanes share the single forwarded clock, inter-lane skew must be managed — the de-skew budget is one of the first things you check when a 4-lane link works at 2 lanes but corrupts at 4.
| Mode | Signaling | Swing | Typical rate | Purpose |
|---|---|---|---|---|
| HS | Differential | ~200 mV | 0.8–4.5 Gbps/lane | Pixel / packet payload |
| LP | Single-ended | 0–1.2 V | ≤ 10 MHz | Control, turnaround, escape |
| ULPS | LP-00 held | ~0 V | — | Deep idle, lowest power |
Anatomy of a burst
A HS transmission is a carefully choreographed sequence of LP states and HS timing parameters you will meet in every D-PHY spec and simulation log:
- LP-11 → LP-01 → LP-00: the transmit request handshake on the data lane.
- THS-PREPARE: driver enables HS, line settles.
- HS-SYNC (00011101): the sync byte that aligns the receiver's byte boundary before payload bytes stream.
- THS-TRAIL → LP-11: graceful exit back to idle.
Getting THS-PREPARE, THS-ZERO, and THS-TRAIL inside spec is the classic bring-up headache — a clock lane that leaves HS a few nanoseconds too early truncates the last byte of every line. Engineers validate these on an oscilloscope eye diagram and in pre-silicon with Synopsys VCS/Verdi testbenches, Cadence Palladium emulation, or protocol-aware analyzers; Siemens (Mentor) HyperLynx is commonly used for the channel SI budget on the flex. For an introduction to how CSI-2 packets ride on top of these bursts, see our MIPI protocol basics primer.
Power: why the dual mode matters
Camera traffic is bursty. A sensor streams a line of pixels, then goes quiet during horizontal/vertical blanking. If the differential HS drivers stayed active during every blanking interval, a 4-lane link would waste tens of milliwatts doing nothing. Instead the lanes drop to LP-11 between lines and to ULPS between frames, where static current is essentially leakage only. This is why D-PHY beats a generic LVDS link for mobile: the energy-per-bit is excellent during the burst and the idle current is near zero. In an always-on front camera for face unlock, that idle behavior is the difference between hours and days of standby.
Rule of thumb: HS mode optimizes energy-per-bit while transmitting; LP and ULPS optimize energy during the (often majority) time the link is idle. D-PHY wins by having both.
D-PHY versus its siblings
MIPI also defines C-PHY (three-wire trios with embedded clock and 16-into-7-symbol coding, higher bandwidth per pin) and M-PHY (used by UniPro/UFS and embedded-clock SerDes). D-PHY's forwarded-clock simplicity keeps PHY design and PLL requirements modest, which is why it remains the default for cost-sensitive sensors and displays even as C-PHY wins the highest-resolution flagships. Choosing between them for a new SoC is a real design trade — our design-services partner Avecas VLSI design services evaluates exactly these PHY/pin-count/bandwidth trade-offs on live silicon programs. For the register-and-packet view of the layer above, continue to our CSI-2 packet format deep dive.
Where this shows up in interviews and real work
Expect questions like: "Why is the clock DDR?" (to halve the clock-lane frequency for a given data rate), "What is LP-00 used for?" (escape/ULPS entry and part of the HS request handshake), and "How does the RX byte-align?" (the HS-SYNC 00011101 pattern). Being able to sketch the block diagram above and narrate one full burst is a strong signal in any SoC interface or display/camera subsystem role. Our VLSI protocol courses drill these with waveform exercises and real analyzer captures.
Ready to master camera and display interfaces end to end? Join CourseTron's MIPI & High-Speed Protocols course — hands-on D-PHY, C-PHY, CSI-2 and DSI with scope captures and simulation labs.
Frequently asked questions
Does every D-PHY link need a separate clock lane?
Yes. D-PHY is source-synchronous, so there is always one dedicated clock lane forwarding a DDR clock to strobe the data lanes. This differs from C-PHY and M-PHY, which embed the clock in the data and recover it at the receiver, saving a lane pair at the cost of PHY complexity.
What is the maximum data rate of D-PHY?
It depends on the spec version. Classic D-PHY v1.x lanes run up to about 1.5–2.5 Gbps per lane; D-PHY v2.1 reaches 4.5 Gbps and v2.5 pushes toward 9 Gbps per lane with signal-processing options. With four data lanes, aggregate HS throughput easily exceeds 10 Gbps, enough for high-resolution, high-frame-rate sensors.
Why use two signaling modes instead of one?
HS differential signaling is energy-efficient and low-EMI while data is actively moving, but its terminated drivers waste power when idle. LP single-ended signaling and ULPS let the lane drop to near-zero current between bursts. Because camera and display traffic is bursty, the combination minimizes total energy across both active and idle time.
Is D-PHY used only for cameras?
No. The same D-PHY carries CSI-2 for cameras and DSI for displays. The electrical layer is shared; only the protocol packets riding on top differ, which is why mastering D-PHY pays off across the entire mobile and automotive imaging pipeline.