In short: AMBA CHI is Arm's packet-switched, layered coherency protocol that lets dozens or hundreds of caching agents share memory correctly by exchanging snoops and MOESI-style cache states over a scalable interconnect, succeeding ACE where a bus-style fabric runs out of headroom.
If you have ever wondered how a 128-core server SoC keeps every private L1 and L2 cache consistent without grinding to a halt, the answer on most modern Arm-class silicon is the Coherent Hub Interface (CHI). CHI is the high-end member of the AMBA family, sitting a tier above the bus-oriented AXI and ACE protocols. Where AXI defines five independent read/write channels for a single master talking to memory, CHI defines a credited, packet-based transport designed from the start for many-core coherency across a mesh.
Why a bus could not scale
AMBA ACE (the coherency extension to AXI) works well for a handful of clusters, but it carries coherency on top of AXI's address/data handshakes and relies on broadcast-style snoop channels. Once you push past roughly 8-16 fully coherent masters, the shared-channel contention, the wiring cost of a crossbar, and the snoop fan-out become the bottleneck. CHI solves this by making the interconnect a network: transactions are packets, flows are decoupled, and the physical fabric is typically a 2D mesh of routers (Arm's CMN-700, for example, scales to hundreds of mesh cross-points).
Fact: A CHI request like a ReadShared is a single flit on the REQ channel carrying a transaction ID (TxnID). The response data may return many cycles later on a different channel, correlated only by that ID — this decoupling is what lets one agent keep ~256 outstanding transactions in flight.
The agents and the channels
CHI defines a small set of node types. Understanding them is the key interview question:
- RN-F (Request Node, Fully coherent) — a CPU cluster with caches that both issues requests and answers snoops.
- RN-I / RN-D — I/O-coherent or DVM request nodes that issue requests but hold no coherent cache.
- HN-F (Home Node, Fully coherent) — the point of coherency and serialization for a memory region; it owns the snoop filter / directory.
- SN-F (Slave Node) — the memory controller or memory-side endpoint behind the home node.
Traffic flows over distinct channels — REQ (requests), RSP (responses), SNP (snoops, sent from home node to request nodes), and DAT (data). Keeping snoops on their own channel is what prevents a snoop storm from blocking fresh requests.
Cache states: MOESI, CHI-style
CHI line states are a superset of MESI, closely matching MOESI, encoded as the pair of Unique/Shared and Clean/Dirty plus an Invalid state. The seven useful states are I, SC, SD, UC, UD, UCE, and UDP. The two axes carry real meaning: "Unique" means this cache is the only holder and may write silently; "Dirty" means this cache owes the value back to memory.
| State | Meaning | Can write silently? | Owes writeback? |
|---|---|---|---|
| I | Invalid | No | No |
| SC | Shared Clean | No | No |
| SD | Shared Dirty (owner) | No | Yes |
| UC | Unique Clean | No (needs permission) | No |
| UD | Unique Dirty | Yes | Yes |
Fact: The "SD" (Shared Dirty) state is CHI's equivalent of MOESI's Owned state. It lets one sharer hold the dirty copy and forward it to requesters directly, avoiding a round-trip to DRAM — a direct-cache-to-cache transfer that can cut effective miss latency from ~120 ns to ~40 ns on a large mesh.
A worked snoop sequence
Suppose CPU-0 holds a line in UD (Unique Dirty) and CPU-1 issues a ReadShared for the same address. The flow is: CPU-1 sends ReadShared on REQ to the home node. The home node checks its snoop filter, sees CPU-0 as the holder, and sends SnpShared on SNP to CPU-0. CPU-0 downgrades UD→SD, returns the dirty data on DAT (SnpRespData), and the home node forwards that data to CPU-1, which installs it as SC. No DRAM access was needed. The home node updates its directory so both sharers are tracked.
DVM, atomics, and the modern extensions
CHI carries more than cache lines. DVM (Distributed Virtual Memory) messages broadcast TLB and branch-predictor invalidations across the mesh — essential when an OS unmaps a page shared by many cores. Later revisions (CHI-B through CHI-E and the newer CHI-F/G issue letters) added near-memory atomic operations (so an atomic add executes at the home node without dragging the line into a cache), cache stashing (a producer can push data into a consumer's cache to pre-warm it), and persistent-memory ordering (CleanSharedPersist). These are the features that make CHI attractive for accelerators and SmartNICs, not just CPU clusters.
Verifying CHI in practice
Because CHI has a huge legal-protocol state space, nobody signs off a design by hand. Teams lean on commercial verification IP: Synopsys VC VIP for CHI, Cadence's Verification IP, and Siemens EDA (Questa/Mentor) CHI VIP all provide bus-functional models, a protocol checker, and coverage models that flag illegal flit sequences and deadlock-prone credit scenarios. Formal apps (Cadence Jasper, Synopsys VC Formal) are routinely used to prove the interconnect cannot deadlock. For the physical mesh, congestion and latency are modeled against the CMN interconnect's performance monitors. If you are building these verification and design skills, hands-on VLSI programs such as ChipXpert's VLSI training walk through exactly this kind of protocol bring-up.
To go deeper on the transport layer that CHI inherits, our companion piece on AMBA ACE and bus-based coherency is a useful contrast, and the AXI channel model explains the handshake primitives CHI's packets ultimately map onto.
Want to master interconnect protocols end to end — from AXI handshakes to CHI snoop filters and mesh verification? Explore the protocol and SoC-integration tracks on CourseTron's course catalog.
Frequently Asked Questions
What is the difference between ACE and CHI?
ACE extends AXI's channel-based bus with coherency signals and works for a modest number of clusters. CHI replaces the bus model with a layered, credited, packet-switched protocol over a mesh, enabling far higher core counts and outstanding-transaction depth without a crossbar bottleneck.
What cache states does CHI use?
CHI uses a MOESI-equivalent set: Invalid, Shared Clean, Shared Dirty (the Owned state), Unique Clean, and Unique Dirty, plus the UCE/UDP empty-data states. The Unique axis controls write permission and the Dirty axis controls writeback obligation.
What is the Home Node in CHI?
The Home Node (HN-F) is the point of coherency and serialization for a memory region. It owns the snoop filter or directory, decides which request nodes to snoop, orders conflicting accesses, and forwards data between caches and memory.
Does CHI require DRAM access on every miss?
No. If another cache holds the line in a Unique or Shared Dirty state, the Home Node snoops that cache and forwards the data directly (cache-to-cache), skipping DRAM entirely and cutting latency substantially.