AXI protocol

In short: The AXI protocol is ARM's AMBA interface for connecting high-performance IP blocks on an SoC. It uses five independent channels and a simple VALID/READY handshake so address, data and response traffic can flow at the same time, supporting bursts, outstanding and out-of-order transactions. This guide covers the channels, the handshake, burst types, outstanding transactions and the AXI4, AXI4-Lite and AXI4-Stream variants.

What is the axi protocol?

The axi protocol (Advanced eXtensible Interface) is the high-bandwidth, point-to-point interconnect specification in ARM's AMBA family. It replaces the older shared-bus thinking of AHB and APB with a channel-based, pipelined design: a manager (master) talks to a subordinate (slave) over several dedicated wire groups that each move in one direction and operate independently.

Because address issue, data transfer and completion response are decoupled, an AXI manager can send a read address, keep issuing more addresses, and receive data back later, all without stalling the whole bus. This decoupling is why AXI underpins CPUs, GPUs, DDR controllers and DMA engines in virtually every modern SoC.

The five channels

A full AXI4 interface is built from five channels. Three serve writes, two serve reads:

• AW — Write Address: manager drives the target address, burst length, size and type.
• W — Write Data: carries the write payload plus per-byte WSTRB strobes and a WLAST marker.
• B — Write Response: subordinate returns OKAY/SLVERR/DECERR to confirm the write.
• AR — Read Address: manager drives the read address and burst attributes.
• R — Read Data: subordinate returns data beats plus a response code and RLAST.

The VALID/READY handshake

Every channel moves information one beat at a time using a two-wire handshake. The source asserts VALID when it has placed stable data on the bus; the destination asserts READY when it can accept it. A transfer happens on the single rising clock edge where both VALID and READY are high.

Three rules make this robust and deadlock-free:

1. A source must not wait for READY before asserting VALID.
2. A destination may wait for VALID before asserting READY.
3. Once VALID is asserted it must stay asserted until the handshake completes — the source cannot retract it.

The animation below shows a data beat being accepted only at the instant both signals overlap.

Burst types and transfers

AXI is burst-based: one address phase launches up to 256 data beats. The AxBURST field selects how the address advances across the burst:

• FIXED: the address stays constant for every beat — ideal for reading or writing a single FIFO or peripheral register repeatedly.
• INCR: the address increments by the transfer size each beat — the default for ordinary memory access.
• WRAP: the address increments but wraps at an aligned boundary — used for cache-line fills so the critical word arrives first.

Each beat also carries AxSIZE (bytes per beat), AxLEN (beat count minus one) and, on writes, WSTRB byte strobes that allow partial, unaligned or sparse writes within a beat. A burst must not cross a 4 KB address boundary — a constraint that keeps address decoding inside a single slave region.

Outstanding and out-of-order transactions

Because the address and data channels are independent, an AXI manager can issue a new transaction before earlier ones have completed. These in-flight requests are called outstanding transactions, and the maximum number is a design parameter set by the manager's logic depth and buffering.

AXI optionally tags each transaction with an ID (AxID, BID, RID). Transactions that share an ID must complete in order, but transactions with different IDs may complete out of order. This lets a slow DDR access overtake nothing in its own stream while a faster SRAM read with a different ID returns first — raising effective throughput and hiding memory latency. (Note that AXI4 removed write-data interleaving that earlier AXI3 permitted.)

AXI4, AXI4-Lite and AXI4-Stream

The AXI4 generation defines three interface flavours for different needs:

• AXI4 (full): the complete protocol with bursts up to 256 beats, IDs and out-of-order support. Used for memory-mapped, high-throughput paths like DDR and DMA.
• AXI4-Lite: a stripped-down, memory-mapped variant with no bursts (single beat), no IDs and a fixed data width. Perfect for register banks and simple control/status interfaces where simplicity beats bandwidth.
• AXI4-Stream: an address-less, point-to-point flow for continuous data such as video pixels, radio samples or packet streams. It keeps only the handshake plus TDATA, TVALID, TREADY, TLAST and optional TKEEP/TUSER sidebands.

The rule of thumb: use AXI4 for memory, AXI4-Lite for configuration registers, and AXI4-Stream for data-flow pipelines that never need to address a location.

axi protocol — FAQ

Is AXI a shared bus or point-to-point?

AXI is point-to-point between one manager and one subordinate. Multiple masters and slaves connect through an AXI interconnect or crossbar that arbitrates and routes transactions, but each AXI link itself is a dedicated pair.

Why does AXI use five separate channels?

Separating address, data and response into independent one-way channels lets them operate concurrently and be pipelined. A manager can stream addresses while data from earlier requests is still returning, which is impossible on a single shared bus.

What is the difference between AXI4-Lite and AXI4?

AXI4-Lite drops bursts, transaction IDs and out-of-order support, allowing only single-beat transfers. It trades bandwidth for a much smaller, simpler implementation, which suits control and status registers rather than bulk data movement.

Does AXI4-Stream use addresses?

No. AXI4-Stream has no address channel at all. It is a unidirectional flow controlled purely by TVALID/TREADY, with TLAST marking packet boundaries — designed for continuous data rather than memory-mapped access.

Related: AXI vs AHB vs APB · Glossary · all courses.