In short: An AXI burst is one address handshake followed by multiple data transfers (beats); FIXED keeps the address constant, INCR steps it by the transfer size each beat, and WRAP steps it but rolls the address back inside an aligned, power-of-two window so a cache line can be refilled critical-word-first without a second address phase.
If you have ever read an AXI waveform and wondered why a read of a 64-byte cache line issues the addresses out of order, the answer is burst types. The AMBA AXI protocol lets a master send a single address, a length, a size and a burst type, and the slave then streams the data. Getting the three types right — FIXED, INCR and WRAP — is the difference between a DMA engine that saturates a DDR controller and one that stalls it. This article walks through the mechanics, the arithmetic, and why interviewers love WRAP.
Beats, bursts and the address channel
AXI separates address from data. A read starts when the master drives ARADDR, ARLEN, ARSIZE and ARBURST and the slave accepts with ARREADY. That is one address handshake. The slave then returns ARLEN+1 data transfers on the R channel — each transfer is a beat. A burst is simply the whole group of beats produced by that one address phase.
- ARSIZE/AWSIZE encodes bytes per beat as a power of two:
0b011= 8 bytes,0b101= 32 bytes. The size must not exceed the data-bus width. - ARLEN/AWLEN is beats minus one. In AXI4 a normal INCR burst can be up to 256 beats (
ARLEN= 0..255); FIXED and WRAP are capped at 16 beats. - ARBURST/AWBURST selects the type:
00FIXED,01INCR,10WRAP,11reserved.
Crucially, a burst must never cross a 4 KB boundary. That rule exists because 4 KB is the smallest page granularity, so a single burst always lands in one page and one slave decode region. A DMA descriptor that asks for 8 KB is therefore split by the interconnect (for example an Arm CoreLink NIC-400 or an AXI crossbar generated in Cadence/Synopsys flows) into two or more bursts.
FIXED: same address every beat
In a FIXED burst the slave uses the same address for every beat. The transfer size still applies, but the address never advances. This is exactly what you want for a memory-mapped FIFO or a peripheral data register: draining a UART receive FIFO means reading the same RBR offset 16 times, not 16 consecutive bytes. FIXED keeps the pointer parked while the hardware supplies fresh data each cycle.
FIXED is for registers and FIFOs, not for RAM. Using FIXED against DRAM would read the same word repeatedly and is almost always a design bug caught in simulation (VCS, Xcelium or Questa) long before silicon.
INCR: the workhorse
INCR increments the address by the number of bytes per beat (2^ARSIZE) after each transfer. It is the default for any block move through memory — linear DMA, instruction prefetch, memcpy. There is no alignment or window constraint beyond the 4 KB rule, and the length can reach 256 beats, so a 32-byte-wide bus can move 8 KB... except the 4 KB rule caps one INCR burst at that page, so the practical maximum useful payload per burst is 4 KB.
Worked example: a 64-bit (8-byte) bus, ARSIZE=3, ARLEN=7 (8 beats), starting at 0x1000. The beat addresses are 0x1000, 0x1008, 0x1010, ... 0x1038 — a clean 64-byte linear fill. Interconnect schedulers and DDR controllers love INCR because consecutive addresses map to the same open DRAM row, maximising row-buffer hit rate.
WRAP: critical-word-first cache refill
WRAP is where AXI earns its reputation. It behaves like INCR — the address increments by the transfer size each beat — but when the address reaches the top of an aligned, power-of-two boundary it wraps back to the lower boundary of that window. The window size equals number_of_beats × bytes_per_beat, and the start address must be aligned to the transfer size. The length is restricted to 2, 4, 8 or 16 beats precisely so the window is always a power of two.
Why do this? A CPU cache miss wants the specific word it faulted on first so the pipeline can resume, while the rest of the line fills in the background. With WRAP the master issues the start address of the needed word, receives it on beat 0, and the slave wraps around to deliver the remaining words of the line — a single address phase refills the whole line, critical-word-first, with zero wasted cycles.
Comparing the three at a glance
| Type | ARBURST | Address per beat | Max beats | Typical use |
|---|---|---|---|---|
| FIXED | 00 | Constant | 16 | Peripheral FIFO / register port |
| INCR | 01 | +2^SIZE each beat | 256 | Linear DMA, memcpy, prefetch |
| WRAP | 10 | +2^SIZE, wraps in aligned window | 16 (2/4/8/16 only) | Cache-line refill, critical-word-first |
Outstanding transactions and why they matter
Burst type controls what one transaction looks like; outstanding transactions control how many are in flight at once. Because AXI decouples address and data and tags every transaction with an ID, a master can issue AR for transaction A, then AR for B and C, before any R data returns. The number of IDs and the depth of the interconnect's transaction trackers set the ceiling.
Outstanding depth hides memory latency. If a DDR read has 100 ns of latency and each burst moves 64 bytes, a single outstanding burst caps you near 0.6 GB/s; allowing 8 outstanding bursts multiplies effective bandwidth roughly 8× until the DRAM, not the protocol, becomes the limit.
Responses for a given ID must return in order, but different IDs may interleave and complete out of order. This is why a high-performance master — say a GPU texture unit or a networking accelerator built with Avecas VLSI design services — spreads reads across many IDs: it lets a fast SRAM response overtake a slow DRAM one instead of head-of-line blocking the whole pipe. Verification engineers model exactly this with scoreboards in UVM testbenches under Siemens Questa or Synopsys VCS.
Common mistakes and how tools catch them
- Crossing 4 KB. A protocol checker (e.g. an AXI VIP assertion in Cadence Xcelium) fires immediately. Split the burst.
- Unaligned WRAP start. The start address must be size-aligned; otherwise the wrap window is undefined. Formal tools flag it.
- WRAP length not 2/4/8/16. Only these keep the window a power of two.
- FIXED against memory. Functionally legal, almost always wrong — you overwrite or re-read one location.
For a protocol-level refresher on the channels and handshakes underneath all of this, see our companion piece on the AXI protocol explained, and for the lighter sibling bus used on peripherals, read AXI-Lite vs AXI-Full.
Want to design and verify AXI masters, slaves and interconnects hands-on — writing UVM scoreboards and running real bursts in VCS/Questa? Explore the protocols and verification tracks on the CourseTron courses page, or deepen your RTL skills with ChipXpert's VLSI training.
FAQ
What is the difference between a beat and a burst in AXI?
A beat is a single data transfer (one valid/ready handshake on the data channel). A burst is the whole set of beats produced by one address handshake; its length is ARLEN+1 (or AWLEN+1) beats.
Why is WRAP limited to 2, 4, 8 or 16 beats?
WRAP wraps inside an aligned power-of-two window whose size is beats × bytes-per-beat. Restricting the count to powers of two guarantees the window boundary is a clean power-of-two address, which is exactly how cache lines are organised.
Can an AXI burst cross a 4 KB boundary?
No. The spec forbids it so every burst stays within one 4 KB page and one decode region. Masters or the interconnect must split any access that would cross the boundary into separate bursts.
How do outstanding transactions differ from burst length?
Burst length is how many beats one transaction carries. Outstanding transactions is how many separate transactions are in flight simultaneously. Longer bursts amortise address overhead; more outstanding transactions hide memory latency — you usually tune both.